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Author SHA1 Message Date
Thomas Fleming
97e9baa316 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Ross Thompson
a982ad7a9a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Ross Thompson
7902c3fdb6 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Katherine Parry
5374dca1b9 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a fixed various bugs 2021-03-04 22:18:19 +00:00
Ross Thompson
5b7f0772ca Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 16:06:22 -06:00
Brett Mathis
b5a08e496f Pipelined functional units for FPU 2021-03-04 14:30:11 -06:00
Thomas Fleming
38bd683f2d Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Thomas Fleming
c6a80c17e5 Add reference output for mmu test 2021-03-04 15:17:49 -05:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Thomas Fleming
97da55e7ce Fix some constants in virtual memory test 2021-03-04 13:19:55 -05:00
bbracker
7852d866ef JALR testing 2021-03-04 10:37:30 -05:00
bbracker
5de23fcbe0 changed test maker to output trace files for debug 2021-03-04 10:36:04 -05:00
Ross Thompson
d0223da2f7 Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120 Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24 Fix to 32-bit option of commit 2d40898158 2021-03-04 01:33:34 -06:00
Thomas Fleming
d821a1dbfa Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956 Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Thomas Fleming
692d4152fa Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Thomas Fleming
5fd521d333 Create virtual memory ad-hoc test 
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
 2021-03-03 17:06:37 -05:00
Teo Ene
d3a1afe50e Fix to last push 2021-03-03 15:20:38 -06:00
Teo Ene
b50faef94d Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e30645a4f1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-02 17:23:44 -06:00
Teo Ene
d02e22feac Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
David Harris
23a1cf63b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
6f4e8b723e Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
2d40898158 Properly implemented the fix from commit 5fee65231e 2021-02-28 22:22:04 -06:00
Noah Boorstin
a5f1dbfe23 add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
Brett Mathis
87e4311339 Fcmp/Fsgn pipeline modules 2021-02-25 18:22:30 -06:00
David Harris
bad180fc15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2 Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b Fixed previous commit 2021-02-25 11:24:44 -06:00