17 Commits

Author	SHA1	Message	Date
bbracker	9c3cb0d2bf	peripheral lint fixes	2021-06-10 10:19:10 -04:00
bbracker	f0266f621b	merge	2021-06-10 10:03:01 -04:00
bbracker	58d0e46d02	UART improved and added more reg read side effects	2021-06-10 09:53:48 -04:00
David Harris	9dd3857c26	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
bbracker	5026a42fac	* GPIO comprehensive testing ... * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr	2021-06-08 12:32:46 -04:00
David Harris	96e90402c5	Rolled back fflush on uart. Use -syncio in Modelsim command line instead.	2021-05-03 20:04:44 -04:00
David Harris	062120f944	Flush uart print statements on \n	2021-05-03 19:51:51 -04:00
David Harris	743011194b	Flush uart print statements on \n	2021-05-03 19:41:37 -04:00
David Harris	8758b6efa1	Flush uart print statements on \n	2021-05-03 19:37:45 -04:00
David Harris	1f2da4c457	Flush uart print statements on \n	2021-05-03 19:25:28 -04:00
bbracker	5687ab1c96	do script refactor	2021-04-24 09:32:09 -04:00
bbracker	195cead01c	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
bbracker	62dd9e3075	first merge of ahb fix	2021-03-05 14:24:22 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
bbracker	deb7780897	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00