David Harris
6e0b0487dd
Recreated coverage changes
2024-09-05 16:32:45 -07:00
David Harris
712274af3d
Removed covergen makefile
2024-09-05 16:29:07 -07:00
David Harris
941d662b59
Removed covergen
2024-09-05 16:28:48 -07:00
Jordan Carlin
57be462a9f
Merge pull request #946 from ross144/main
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Fixes missing logic declaration in spi_apb.sv
2024-09-05 12:52:33 -07:00
Rose Thompson
32624bc6ee
Relocated a logic in a file to avoid a future merge conflict.
2024-09-05 12:50:09 -07:00
Rose Thompson
005ea52b72
Added missing signal declaration for SPI.
2024-09-05 12:20:06 -07:00
Rose Thompson
4e2e922c39
Merge branch 'main' of github.com:openhwgroup/cvw
2024-09-05 12:09:19 -07:00
Rose Thompson
510e3a268c
Added spi debugger to build script.
2024-09-05 12:04:14 -07:00
Rose Thompson
261e503061
Updates for arty A7 device tree.
2024-09-05 12:02:07 -07:00
Jordan Carlin
9f5c320a93
Merge pull request #944 from davidharrishmc/dev
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WallyTracer fix
2024-09-05 00:24:50 -07:00
David Harris
9eb7869205
Merge pull request #942 from ross144/main
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Improved automated support for FPGAs
2024-09-04 17:57:01 -07:00
Rose Thompson
ac047a04fa
Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test
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if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI
flash card now correctly loads into the Linux OS and mount and is
reading and writting without error.
2024-09-04 17:51:48 -07:00
Rose Thompson
8c99e28c8b
Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script.
2024-09-03 21:03:38 -07:00
Rose Thompson
33435bfb6a
Merge branch 'main' of github.com:openhwgroup/cvw
2024-09-03 15:16:13 -07:00
Rose Thompson
36d2d7aba5
Merge pull request #943 from naichewa/main
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SPI SckDiv = 0 bug fix
2024-09-03 15:14:46 -07:00
naichewa
58be9e0556
Merge branch 'spi_debug'
2024-09-03 15:00:59 -07:00
naichewa
3b7661dfd5
SckDiv Zero bug fixes
2024-09-03 14:58:46 -07:00
Rose Thompson
f4b5664cc6
Merge branch 'main' of github.com:openhwgroup/cvw
2024-09-03 13:12:00 -07:00
Rose Thompson
f22f056b09
This actually fixes the vcu108 to correctly set the SPI clock frequency.
2024-09-03 13:11:03 -07:00
Rose Thompson
c24d061d0a
Fixed typo in fpga Makefile.
2024-09-03 12:19:16 -07:00
Rose Thompson
8248f2dd66
Added MAXSDCCLOCK to parameters set by the FPGA makefile.
2024-09-03 10:55:15 -07:00
Rose Thompson
d0ae6bf217
Fixed type in fpga Makefile
2024-09-03 10:36:49 -07:00
Rose Thompson
cde4598ed5
Updated vcu108 and vcu118 scripts to corrects set the clock speed.
2024-09-03 10:31:55 -07:00
Rose Thompson
702fa4e7bd
Finally worked out that subtle bug in the tcl scripts clock setting.
2024-09-03 10:30:34 -07:00
David Harris
ff9f0fa140
Updated riscv-isac dependencies for security
2024-09-03 03:46:44 -07:00
David Harris
b670f700ec
Test push
2024-09-03 03:37:33 -07:00
Rose Thompson
e29e1feed5
Corrects merge error in Arty A7 clock speed.
2024-09-02 15:01:41 -07:00
Rose Thompson
8375e168c0
Removed file accidently readded.
2024-09-02 14:48:36 -07:00
Rose Thompson
3a0e28fea0
Added missing spi debugger.
2024-09-02 14:47:31 -07:00
Rose Thompson
4afdb500d7
Added missing files.
2024-09-02 14:46:41 -07:00
Rose Thompson
d5e0382a81
vcu108 build now starts with make vcu108 and selects the correct
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memory size, starting address, device tree location, and clock speed
for the zsbl and synthesis scripts.
2024-09-02 14:23:16 -07:00
Rose Thompson
869860bc55
Merge branch 'main' of github.com:ross144/cvw
2024-09-02 14:08:48 -07:00
Rose Thompson
9471ccd2fc
Updated Makefiles and source files to build the zsbl according to the config.
2024-09-02 14:03:47 -07:00
Rose Thompson
2e55f1cecc
Well on the way to a fully automated FPGA build process which
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correctly sets the clocks and memory locations.
2024-09-02 11:19:02 -07:00
David Harris
5af07db76c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-08-31 16:20:05 -07:00
David Harris
4f8fedad2e
README update
2024-08-30 13:37:18 -07:00
Jordan Carlin
0200b08418
Merge pull request #940 from ross144/main
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Merges Jordan's wally.do updates with the new fcov2 changes.
2024-08-30 12:35:11 -07:00
Jordan Carlin
9e98c834f1
Add lockstepverbose flag
2024-08-30 12:32:41 -07:00
Rose Thompson
65e338e762
Merges Jordan's wally.do updates with the new fcov2 changes. Updates
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cvw-arch-verif commit.
2024-08-30 12:31:26 -07:00
Rose Thompson
6f7d4cde21
Merge pull request #908 from jordancarlin/script_updates
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Sim updates + rv64gcCacheSim.py fixed
2024-08-30 12:25:44 -07:00
Rose Thompson
5fb3b386f5
Merge pull request #939 from JacobPease/main
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Fixed Arty constraints and corrected typos.
2024-08-30 12:23:53 -07:00
Jacob Pease
4b8d35bd8a
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-30 14:18:54 -05:00
Jacob Pease
4acac08320
Fixed Arty constraints and corrected typos.
2024-08-30 14:17:37 -05:00
Jordan Carlin
4929581576
Cleanup
2024-08-30 11:57:31 -07:00
Rose Thompson
f1d9e18dee
Modified fpga config to support two fpga boards with different amount of memory.
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Modified vcu108 constraints to better constrain the spi clock and in/out.
2024-08-29 16:12:58 -07:00
Jordan Carlin
80750f2308
Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
2024-08-29 15:55:54 -07:00
David Harris
a9d904caf1
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-08-29 15:43:04 -07:00
David Harris
ffd4d71fe5
Merge pull request #938 from ross144/main
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Fixed basic support for open source riscvISACOV
2024-08-29 15:42:40 -07:00
Rose Thompson
587a65aa75
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-29 15:30:45 -07:00
Rose Thompson
e07f303353
Have basic rv32gc functional coverage running with open source riscvISACOV.
2024-08-29 15:29:04 -07:00
