Jacob Pease
f1cc7dd5a3
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Jacob Pease
dcb2edf888
Fixed syntax bugs. inline functions are now static and in the spi.h header.
2024-07-23 17:00:32 -05:00
Rose Thompson
e8e71ad643
Code cleanup.
2024-07-23 16:35:05 -05:00
Jacob Pease
5f0addd69a
Initial pass on SPI based bootloader code finished.
2024-07-23 16:33:49 -05:00
Jacob Pease
a8b9e7776b
Added some minor error checking to gpt.c.
2024-07-23 16:32:52 -05:00
Jacob Pease
ab00ea5a5c
Added sd_read64 to help with block reads and crc checking.
2024-07-23 16:32:29 -05:00
Rose Thompson
57ea39d685
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
54e0289608
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Jacob Pease
57eeba5c8c
Progress made on implementing new disk read function.
2024-07-23 15:47:23 -05:00
Jacob Pease
9ccb0eb027
Removed references to card_type.
2024-07-23 15:46:18 -05:00
Jacob Pease
d9afaade03
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-23 14:18:50 -05:00
Jacob Pease
bf65cd2817
Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
2024-07-23 14:18:42 -05:00
Rose Thompson
1eff86b7ae
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
825dbefcb2
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
42f2469ea7
Merge pull request #891 from davidharrishmc/dev
...
Increased covergen.py functional coverage to 87.6%
2024-07-23 09:34:13 -05:00
David Harris
a4a0a10879
Increased covergen.py functional coverage to 87.6%
2024-07-23 04:38:13 -07:00
Rose Thompson
94a1ce32e7
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
8ca565ed53
Updated for a better ILA rvvi debugger.
2024-07-22 17:44:04 -05:00
Jacob Pease
b05052311f
Added sd_cmd and utility SPI functions.
2024-07-22 16:57:04 -05:00
Rose Thompson
121342f4cc
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Jacob Pease
6a9141e3be
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-22 13:06:05 -05:00
Jacob Pease
cec39fd3aa
Added new SDC clock constraint.
2024-07-22 13:05:16 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Rose Thompson
00c30239bf
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
556c210e76
Added option to use rvvi ila
2024-07-22 12:19:37 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
32903a38f5
Merge pull request #890 from davidharrishmc/dev
...
Fixed argument name in regression-wally
2024-07-22 12:00:25 -05:00
David Harris
4c46315907
Fixed argument name in regression-wally
2024-07-22 09:19:56 -07:00
Rose Thompson
844bc01c0a
Merge pull request #889 from davidharrishmc/dev
...
Functional coverage improvements, fix WARL bug on MTVEC/STVEC
2024-07-22 10:59:16 -05:00
David Harris
040b359813
Added more RV64I coverage generation
2024-07-22 08:52:19 -07:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
David Harris
757cc8a5f7
Added QuestaFunctCoverage to merge functional coverage reports
2024-07-22 08:49:54 -07:00
David Harris
c4400dfeb0
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Rose Thompson
d9ef588324
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 10:01:33 -05:00
Jacob Pease
e067e0896f
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-22 01:21:15 -05:00
Jacob Pease
e91d2c8b14
Corrected the CRC7 code with the right sequence of instructions.
2024-07-22 01:19:10 -05:00
David Harris
e949c9cfba
Removed more obsolete imperas scripts
2024-07-21 19:47:23 -07:00
David Harris
da502d2d5a
Fixed makefile log typo
2024-07-21 19:47:00 -07:00
David Harris
af79fd5702
Fixed hazard and rd_maxval coverage generation
2024-07-21 19:46:30 -07:00
David Harris
7fd8c6e29a
Removed outdated wally-imperas files
2024-07-21 19:45:22 -07:00
Jordan Carlin
5687e31c15
Merge pull request #888 from davidharrishmc/dev
2024-07-21 12:04:29 -07:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Jacob Pease
c7d869bc96
Added inital spi based sd card code. Working on CRC7 code that works.
2024-07-20 14:00:43 -05:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642
Updated verilog-ethernet to be compatible with wally.
2024-07-19 13:36:26 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
