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Author	SHA1	Message	Date
Ross Thompson	8bce2fc739	Getting closer.	2024-06-11 16:21:53 -07:00
Ross Thompson	c9f3da51cb	getting closer to full reconstruction of rvvi.	2024-06-11 15:35:35 -07:00
Ross Thompson	3d9f796f21	Better parsing of rvvi.	2024-06-11 14:36:34 -07:00
Ross Thompson	563980443a	Merge branch 'main' into rvvi	2024-06-10 18:10:23 -07:00
Ross Thompson	49912589f5	Added rvviApi.h to rvvidaemon.	2024-06-10 17:57:24 -07:00
Ross Thompson	e16cf9d739	Added Makefile to compile rvvidaemon	2024-06-10 16:56:53 -07:00
Rose Thompson	72c1374d9c	Minor code cleanup.	2024-06-04 15:11:57 -05:00
Rose Thompson	f0ed780745	progress.	2024-06-04 15:11:03 -05:00
Rose Thompson	07d66c246c	Update.	2024-06-04 11:59:17 -05:00
Rose Thompson	08ff88f428	On the way towards complete reconstruction of the RVVI trace.	2024-06-04 11:47:46 -05:00
Rose Thompson	fc62f80407	Closer to fully working hardware tracer.	2024-06-04 11:31:05 -05:00
Rose Thompson	80f98b3223	now have a working ethernet daemon to collect frames and partially decode into RVVI.	2024-06-04 10:20:51 -05:00
Rose Thompson	dc904cdbbb	The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.	2024-06-03 18:10:25 -05:00
Rose Thompson	0ca10e7ee2	Last of the branch predictor signal name updates.	2024-06-02 17:01:51 -05:00
Rose Thompson	04744032d8	Updated more signal names to match book.	2024-06-02 16:59:11 -05:00
Rose Thompson	b45b7ff7d6	Signal name changes to match book.	2024-06-02 16:32:25 -05:00
Rose Thompson	731e1fe08f	Updated spill logic to reflect changes in textbook.	2024-06-02 15:48:42 -05:00
Rose Thompson	3da62558ec	Updated readme.	2024-06-01 11:12:30 -05:00
Rose Thompson	2382677f8f	Got the directory mode wsim working!	2024-06-01 10:56:37 -05:00
Rose Thompson	224b8469ab	Updated readme to reflect changes to wsim.	2024-06-01 09:58:10 -05:00
Rose Thompson	a78093274c	Simplified wsim so it automatically figures out if the second parameter is a testsuite or an elf file.	2024-06-01 09:56:50 -05:00
Rose Thompson	2a6c5a158f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-06-01 09:50:18 -05:00
Rose Thompson	a830bd57f0	Have to reverse the byte order for ethernet frame length.	2024-05-31 17:46:43 -05:00
Rose Thompson	e05ebc30b8	Almost worked out the bugs in packetizer.	2024-05-31 16:48:41 -05:00
Rose Thompson	9ed78b5f08	Merge pull request #818 from JacobPease/main ... Added true bootloader to fpga/zsbl directory.	2024-05-31 15:34:08 -05:00
Jacob Pease	7a417d7a6c	Added true bootloader to fpga/zsbl directory.	2024-05-31 15:28:25 -05:00
Rose Thompson	0dccc6051d	draft of receiving code to unpack the ethernet frames into rvvi.	2024-05-31 13:55:25 -05:00
Rose Thompson	1df3e5239a	This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer. ... wireshark is able to capture the frames and they match the expected data!	2024-05-30 17:57:28 -05:00
Rose Thompson	6a4c8667df	Added new signals to ILA to debug the RVVI tracer. ... The tracer appears to be stuck and the CPU is never getting out of (into reset).	2024-05-30 16:43:25 -05:00
Rose Thompson	ca90c6ba48	Added the ethernet files. These are part of another repo. ... We should remove before mainlining this.	2024-05-30 16:33:49 -05:00
Rose Thompson	38ddbf860e	Fixed bug with mmcm not generating the 4th clock.	2024-05-30 16:19:28 -05:00
Rose Thompson	24ba51370a	Merge pull request #817 from JacobPease/main ... The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 16:16:05 -05:00
Jacob Pease	3f7659c8ad	Removed old fpgaTop.v file.	2024-05-30 16:15:19 -05:00
Jacob Pease	6bf43ebe61	Merge branch 'main' of github.com:openhwgroup/cvw	2024-05-30 15:48:31 -05:00
Jacob Pease	7ecd1c7d5f	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
Rose Thompson	9703055758	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
Rose Thompson	f4626d5b06	Fixed bug so that wsim can start logging after a given number of instructions.	2024-05-29 14:50:09 -05:00
Rose Thompson	84946919a4	Changed name CacheWriteData to WriteData.	2024-05-28 18:00:39 -05:00
Rose Thompson	273b41df99	Changed name of cache parameter NUMLINES to NUMSETS to better match book.	2024-05-28 17:55:43 -05:00
David Harris	44f25186c6	Merge pull request #816 from ross144/main ... Merges support for functional coverage into wally.do and testbench.sv	2024-05-28 21:54:37 +02:00
Rose Thompson	a88d5f403b	Functional coverage works with wally.do	2024-05-28 14:02:54 -05:00
Rose Thompson	0c5b70c40a	It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv.	2024-05-28 13:54:48 -05:00
Rose Thompson	48fd365b9d	Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.	2024-05-28 13:00:17 -05:00
Rose Thompson	4a1e856b18	Almost working functional coverage in wally.do ... riscvISACOV is now loading, but for some reason I still cannot get it to record anything. Instead it is just logging the instructions.	2024-05-27 18:15:12 -05:00
Rose Thompson	92ee56c1a1	Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV. ... testbench.sv was missing the trace2cov instance.	2024-05-27 17:25:20 -05:00
Rose Thompson	4c0261fd2c	Closer. Needed to reorder includes and defines.	2024-05-27 15:37:16 -05:00
Rose Thompson	ff611016c7	Closer?	2024-05-27 14:11:02 -05:00
Rose Thompson	26c6eec832	Getting closer to functional coverage integration.	2024-05-27 13:20:18 -05:00
Rose Thompson	2985cfb7eb	Preliminary work to merge functional coverage into wally.do.	2024-05-27 11:59:13 -05:00
Rose Thompson	c9b59c8b99	Merge pull request #815 from quswarabid/covergen ... Covergen	2024-05-27 10:42:29 -05:00