Ross Thompson
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87485ed237
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Possible fix for ifu/lsu arbiration issue.
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2022-09-27 17:24:35 -05:00 |
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Ross Thompson
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afc6934249
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Possible fix to the bus cache interaction.
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2022-09-27 11:34:33 -05:00 |
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Ross Thompson
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dfe6bdd06d
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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f24b0feeed
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renamed ahbmulticontroller to ebu.
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2022-09-26 14:37:18 -05:00 |
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Ross Thompson
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fd47cf05c3
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-26 12:49:16 -05:00 |
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Ross Thompson
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fd2a8e621a
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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Kip Macsai-Goren
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0d2fcaeab1
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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4fa8b10315
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added simple post processing script to give branch miss proportion in coremark log
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2022-09-26 04:51:04 +00:00 |
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David Harris
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b5d2bbe7ca
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changed always_ff to always in sram1p1rw to fix testbench complaint
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2022-09-25 19:56:40 -07:00 |
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Ross Thompson
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dcc00ef4b3
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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6a6686a34b
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Removed the write first sram model.
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2022-09-22 16:12:08 -05:00 |
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Ross Thompson
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8a6ca027c2
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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29087812e1
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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f74d21e063
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 18:24:06 -05:00 |
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Ross Thompson
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cd5b8be78f
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Cleaned up the IFU and LSU around dtim and irom address calculation.
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2022-09-21 18:23:56 -05:00 |
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David Harris
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cfa83fdd98
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For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
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2022-09-21 13:30:35 -07:00 |
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David Harris
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fce927810a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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f08d5b23d5
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Eliminated store after store stall when no cache; simplified divshiftcalc logic.
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2022-09-21 13:02:34 -07:00 |
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Ross Thompson
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f83d640068
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Updated IROMAdr logic.
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2022-09-21 12:42:43 -05:00 |
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Ross Thompson
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0294ca0469
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:36:52 -05:00 |
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Ross Thompson
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cdc80c1f28
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Moved other SRAMs to generic/mem.
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2022-09-21 12:36:03 -05:00 |
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David Harris
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3b0714b059
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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1c8581dd6d
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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427db1f55f
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Renamed brom1p1r to rom1p1r.
removed used file bram2p1r1w.sv.
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2022-09-21 12:31:20 -05:00 |
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Ross Thompson
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234cf7510e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:20:12 -05:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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d6fa8d51d7
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Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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2022-09-21 11:26:00 -05:00 |
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David Harris
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f87e15388a
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commented SpecialCase
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2022-09-21 05:02:08 -07:00 |
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David Harris
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b21e36a788
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Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc
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2022-09-21 04:55:43 -07:00 |
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David Harris
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437fd52bf6
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Gated sticky bit in fdiv with SpecialCase
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2022-09-20 20:05:00 -07:00 |
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David Harris
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cf5c513221
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Restored radix 2 to pass regression
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2022-09-20 19:30:16 -07:00 |
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David Harris
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9c8edb9cb6
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renamed u to udigit to avoid conflict with U
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2022-09-20 19:29:23 -07:00 |
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cturek
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e8f2715a81
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Fixed R4 Sqrt overshifting
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2022-09-21 00:05:36 +00:00 |
|
cturek
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49a1259cf9
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Fixed fgen4
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2022-09-20 20:00:01 +00:00 |
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Ross Thompson
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c73fae8a96
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Merge branch 'tempMain' into main
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2022-09-20 13:57:38 -05:00 |
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Ross Thompson
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1c2e47e137
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-20 11:56:53 -05:00 |
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Ross Thompson
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b2f4d4aaa7
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Added chip enables to sram.
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2022-09-20 10:49:14 -05:00 |
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David Harris
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33af1f97f7
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Define LOGNORMSHIFTSZ
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2022-09-20 08:31:57 -07:00 |
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Ross Thompson
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7470bf7c7c
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Added comment.
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2022-09-20 09:49:53 -05:00 |
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Ross Thompson
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ea6b687f7c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-20 09:47:16 -05:00 |
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David Harris
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811f498f63
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renamed q to u for unified digit selection
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2022-09-20 04:35:14 -07:00 |
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David Harris
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705a2bd97b
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Removed D2 and D2b from radix2 stage
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2022-09-20 04:20:38 -07:00 |
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David Harris
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c77ec2aa9c
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Simplified UM initialization
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2022-09-20 04:18:12 -07:00 |
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David Harris
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956011b40b
|
fdivsqrtfgen4 comments
|
2022-09-20 04:13:21 -07:00 |
|
David Harris
|
8d1408a9d6
|
Moved fpu modules into subdirectories
|
2022-09-20 04:12:05 -07:00 |
|
David Harris
|
0af8151c2a
|
Partitioned fdivsqrt into one module per file and added file names to opening comments
|
2022-09-20 03:57:57 -07:00 |
|
David Harris
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5b13140078
|
Simplified fdivsqrtpostproc QmM logic
|
2022-09-20 03:30:18 -07:00 |
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David Harris
|
8647de5ee4
|
make QmM size b+1 indpenedent of radix
|
2022-09-20 03:25:09 -07:00 |
|
David Harris
|
31c3b62774
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clean up divshiftcalc
|
2022-09-20 03:19:50 -07:00 |
|
David Harris
|
7177745111
|
clean up divshiftcalc
|
2022-09-20 03:17:29 -07:00 |
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