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renamed q to u for unified digit selection

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This commit is contained in:
David Harris 2022-09-20 04:35:14 -07:00
parent 705a2bd97b
commit 811f498f63
11 changed files with 99 additions and 96 deletions
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6
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -59,7 +59,7 @@ module fdivsqrt(
logic [`DIVN-2:0] Dpreproc;
logic [`DIVb:0] FirstU, FirstUM;
logic [`DIVb+1:0] FirstC;
logic Firstqn;
logic Firstun;
logic WZero;
fdivsqrtpreproc fdivsqrtpreproc(
@ -71,9 +71,9 @@ module fdivsqrt(
.XNaNE, .YNaNE,
.XInfE, .YInfE, .WZero);
fdivsqrtiter fdivsqrtiter(
.clk, .Firstqn, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN,
.DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
.DivBusy);
fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstqn, .SqrtM, .QmM, .WZero, .DivSM);
fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .QmM, .WZero, .DivSM);
endmodule

6
pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh"
module fdivsqrtfgen2 (
input logic sp, sz,
input logic up, uz,
input logic [`DIVb+1:0] C,
input logic [`DIVb:0] U, UM,
output logic [`DIVb+3:0] F
@ -51,8 +51,8 @@ module fdivsqrtfgen2 (
// Choose which adder input will be used
always_comb
if (sp) F = FP;
else if (sz) F = FZ;
if (up) F = FP;
else if (uz) F = FZ;
else F = FN;
endmodule

10
pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh"
module fdivsqrtfgen4 (
input logic [3:0] s,
input logic [3:0] u,
input logic [`DIVb+3:0] C, U, UM,
output logic [`DIVb+3:0] F
);
@ -47,9 +47,9 @@ module fdivsqrtfgen4 (
// Choose which adder input will be used
always_comb
if (s[3]) F = F2;
else if (s[2]) F = F1;
else if (s[1]) F = FN1;
else if (s[0]) F = FN2;
if (u[3]) F = F2;
else if (u[2]) F = F1;
else if (U[1]) F = FN1;
else if (u[0]) F = FN2;
else F = F0;
endmodule

10
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -44,7 +44,7 @@ module fdivsqrtiter(
output logic [`DIVb+3:0] NextWSN, NextWCN,
output logic [`DIVb:0] FirstU, FirstUM,
output logic [`DIVb+1:0] FirstC,
output logic Firstqn,
output logic Firstun,
output logic [`DIVb+3:0] FirstWS, FirstWC
);
@ -66,7 +66,7 @@ module fdivsqrtiter(
logic [`DIVb:0] UMNext[`DIVCOPIES-1:0];// U1.b
logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b
logic [`DIVb+1:0] initC; // Q2.b
logic [`DIVCOPIES-1:0] qn;
logic [`DIVCOPIES-1:0] un;
/* verilator lint_on UNOPTFLAT */
logic [`DIVb+3:0] WSN, WCN; // Q4.N-1
@ -119,13 +119,13 @@ module fdivsqrtiter(
if (`RADIX == 2) begin: stage
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtM,
.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .qn(qn[i]));
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end else begin: stage
logic j1;
assign j1 = (i == 0 & ~C[0][`DIVb-1]);
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1,
.WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]),
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .qn(qn[i]));
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
end
if(i<(`DIVCOPIES-1)) begin
assign WS[i+1] = WSA[i] << `LOGR;
@ -149,6 +149,6 @@ module fdivsqrtiter(
assign FirstU = U[0];
assign FirstUM = UM[0];
assign FirstC = C[0];
assign Firstqn = qn[0];
assign Firstun = un[0];
endmodule

4
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -35,7 +35,7 @@ module fdivsqrtpostproc(
input logic [`DIVN-2:0] D, // U0.N-1
input logic [`DIVb:0] FirstU, FirstUM,
input logic [`DIVb+1:0] FirstC,
input logic Firstqn,
input logic Firstun,
input logic SqrtM,
output logic [`DIVb:0] QmM,
output logic WZero,
@ -60,7 +60,7 @@ module fdivsqrtpostproc(
assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);
assign WZero = weq0|(wfeq0 & Firstqn);
assign WZero = weq0|(wfeq0 & Firstun);
end else begin
assign WZero = weq0;
end

12
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
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@ -32,7 +32,7 @@
module fdivsqrtqsel2 (
input logic [3:0] ps, pc,
output logic qp, qz, qn
output logic up, uz, un
);
logic [3:0] p, g;
@ -42,7 +42,7 @@ module fdivsqrtqsel2 (
// for efficiency. You can probably optimize your logic to
// select the proper divisor with less delay.
// Qmient equations from EE371 lecture notes 13-20
// Quotient equations from EE371 lecture notes 13-20
assign p = ps ^ pc;
assign g = ps & pc;
@ -56,8 +56,8 @@ module fdivsqrtqsel2 (
(ps[1]&pc[1] | ((ps[1]^pc[1]) &
(ps[0]&pc[0])))));
// Produce quotient = +1, 0, or -1
assign qp = magnitude & ~sign;
assign qz = ~magnitude;
assign qn = magnitude & sign;
// Produce digit = +1, 0, or -1
assign up = magnitude & ~sign;
assign uz = ~magnitude;
assign un = magnitude & sign;
endmodule

86
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
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@ -35,7 +35,7 @@ module fdivsqrtqsel4 (
input logic [4:0] Smsbs,
input logic [`DIVb+3:0] WS, WC,
input logic Sqrt, j1,
output logic [3:0] q
output logic [3:0] u
);
logic [6:0] Wmsbs;
logic [7:0] PreWmsbs;
@ -49,7 +49,7 @@ module fdivsqrtqsel4 (
// W = xxxx.xxx...
// Wmsbs = | |
logic [3:0] QSel4[1023:0];
logic [3:0] USel4[1023:0];
always_comb begin
integer a, w, i, w2;
@ -58,46 +58,46 @@ module fdivsqrtqsel4 (
i = a*128+w;
w2 = w-128*(w>=64); // convert to two's complement
case(a)
0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000;
else if(w2>=4) QSel4[i] = 4'b0100;
else if(w2>=-4) QSel4[i] = 4'b0000;
else if(w2>=-13) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
1: if(w2>=14) QSel4[i] = 4'b1000;
else if(w2>=4) QSel4[i] = 4'b0100;
else if(w2>=-4) QSel4[i] = 4'b0000;
else if(w2>=-14) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
2: if(w2>=16) QSel4[i] = 4'b1000;
else if(w2>=4) QSel4[i] = 4'b0100;
else if(w2>=-6) QSel4[i] = 4'b0000;
else if(w2>=-16) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
3: if(w2>=16) QSel4[i] = 4'b1000;
else if(w2>=4) QSel4[i] = 4'b0100;
else if(w2>=-6) QSel4[i] = 4'b0000;
else if(w2>=-17) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
4: if(w2>=18) QSel4[i] = 4'b1000;
else if(w2>=6) QSel4[i] = 4'b0100;
else if(w2>=-6) QSel4[i] = 4'b0000;
else if(w2>=-18) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
5: if(w2>=20) QSel4[i] = 4'b1000;
else if(w2>=6) QSel4[i] = 4'b0100;
else if(w2>=-8) QSel4[i] = 4'b0000;
else if(w2>=-20) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
6: if(w2>=20) QSel4[i] = 4'b1000;
else if(w2>=8) QSel4[i] = 4'b0100;
else if(w2>=-8) QSel4[i] = 4'b0000;
else if(w2>=-22) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
7: if(w2>=24) QSel4[i] = 4'b1000;
else if(w2>=8) QSel4[i] = 4'b0100;
else if(w2>=-8) QSel4[i] = 4'b0000;
else if(w2>=-22) QSel4[i] = 4'b0010;
else QSel4[i] = 4'b0001;
0: if($signed(w2)>=$signed(12)) USel4[i] = 4'b1000;
else if(w2>=4) USel4[i] = 4'b0100;
else if(w2>=-4) USel4[i] = 4'b0000;
else if(w2>=-13) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
1: if(w2>=14) USel4[i] = 4'b1000;
else if(w2>=4) USel4[i] = 4'b0100;
else if(w2>=-4) USel4[i] = 4'b0000;
else if(w2>=-14) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
2: if(w2>=16) USel4[i] = 4'b1000;
else if(w2>=4) USel4[i] = 4'b0100;
else if(w2>=-6) USel4[i] = 4'b0000;
else if(w2>=-16) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
3: if(w2>=16) USel4[i] = 4'b1000;
else if(w2>=4) USel4[i] = 4'b0100;
else if(w2>=-6) USel4[i] = 4'b0000;
else if(w2>=-17) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
4: if(w2>=18) USel4[i] = 4'b1000;
else if(w2>=6) USel4[i] = 4'b0100;
else if(w2>=-6) USel4[i] = 4'b0000;
else if(w2>=-18) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
5: if(w2>=20) USel4[i] = 4'b1000;
else if(w2>=6) USel4[i] = 4'b0100;
else if(w2>=-8) USel4[i] = 4'b0000;
else if(w2>=-20) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
6: if(w2>=20) USel4[i] = 4'b1000;
else if(w2>=8) USel4[i] = 4'b0100;
else if(w2>=-8) USel4[i] = 4'b0000;
else if(w2>=-22) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
7: if(w2>=24) USel4[i] = 4'b1000;
else if(w2>=8) USel4[i] = 4'b0100;
else if(w2>=-8) USel4[i] = 4'b0000;
else if(w2>=-22) USel4[i] = 4'b0010;
else USel4[i] = 4'b0001;
endcase
end
end
@ -107,6 +107,6 @@ module fdivsqrtqsel4 (
else if (Smsbs == 5'b10000) A = 3'b111;
else A = Smsbs[2:0];
end else A = Dmsbs;
assign q = QSel4[{A,Wmsbs}];
assign u = USel4[{A,Wmsbs}];
endmodule

20
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
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@ -38,7 +38,7 @@ module fdivsqrtstage2 (
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtM,
output logic qn,
output logic un,
output logic [`DIVb+1:0] CNext,
output logic [`DIVb:0] UNext, UMNext,
output logic [`DIVb+3:0] WSA, WCA
@ -46,30 +46,34 @@ module fdivsqrtstage2 (
/* verilator lint_on UNOPTFLAT */
logic [`DIVb+3:0] Dsel;
logic qp, qz;
logic up, uz;
logic [`DIVb+3:0] F;
logic [`DIVb+3:0] AddIn;
assign CNext = {1'b1, C[`DIVb+1:1]};
// Qmient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// Given partial remainder, select digit of +1, 0, or -1 (up, uz, un)
// q encoding:
// 1000 = +2
// 0100 = +1
// 0000 = 0
// 0010 = -1
// 0001 = -2
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn);
fdivsqrtfgen2 fgen2(.sp(qp), .sz(qz), .C(CNext), .U, .UM, .F);
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un);
fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F);
always_comb
if (up) Dsel = DBar;
else if (uz) Dsel = '0; // qz
else Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; // un
assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}});
// Partial Product Generation
// WSA, WCA = WS + WC - qD
assign AddIn = SqrtM ? F : Dsel;
csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA);
csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtM, WSA, WCA);
fdivsqrtuotfc2 uotfc2(.sp(qp), .sz(qz), .C(CNext), .U, .UM, .UNext, .UMNext);
fdivsqrtuotfc2 uotfc2(.up, .uz, .C(CNext), .U, .UM, .UNext, .UMNext);
endmodule

21
pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -39,34 +39,33 @@ module fdivsqrtstage4 (
input logic [`DIVb+1:0] C,
output logic [`DIVb+1:0] CNext,
input logic SqrtM, j1,
output logic qn,
output logic un,
output logic [`DIVb:0] UNext, UMNext,
output logic [`DIVb+3:0] WSA, WCA
);
/* verilator lint_on UNOPTFLAT */
logic [`DIVb+3:0] Dsel;
logic [3:0] q;
logic [3:0] u;
logic [`DIVb+3:0] F;
logic [`DIVb+3:0] AddIn;
logic [4:0] Smsbs;
logic CarryIn;
assign CNext = {2'b11, C[`DIVb+1:2]};
// Qmient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// q encoding:
// Digit Selection logic
// u encoding:
// 1000 = +2
// 0100 = +1
// 0000 = 0
// 0010 = -1
// 0001 = -2
assign Smsbs = U[`DIVb:`DIVb-4];
fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .q);
fdivsqrtfgen4 fgen4(.s(q), .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .u);
fdivsqrtfgen4 fgen4(.u, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
always_comb
case (q)
case (u)
4'b1000: Dsel = DBar2;
4'b0100: Dsel = DBar;
4'b0000: Dsel = '0;
@ -78,12 +77,12 @@ module fdivsqrtstage4 (
// Partial Product Generation
// WSA, WCA = WS + WC - qD
assign AddIn = SqrtM ? F : Dsel;
assign CarryIn = ~SqrtM & (q[3] | q[2]); // +1 for 2's complement of -D and -2D
assign CarryIn = ~SqrtM & (u[3] | u[2]); // +1 for 2's complement of -D and -2D
csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
fdivsqrtuotfc4 fdivsqrtuotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
fdivsqrtuotfc4 fdivsqrtuotfc4(.u, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
assign qn = 0; // unused for radix 4
assign un = 0; // unused for radix 4
endmodule

8
pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
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@ -34,7 +34,7 @@
// Unified OTFC, Radix 2 //
///////////////////////////////
module fdivsqrtuotfc2(
input logic sp, sz,
input logic up, uz,
input logic [`DIVb+1:0] C,
input logic [`DIVb:0] U, UM,
output logic [`DIVb:0] UNext, UMNext
@ -46,13 +46,13 @@ module fdivsqrtuotfc2(
assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1));
always_comb begin
if (sp) begin
if (up) begin
UNext = U | K;
UMNext = U;
end else if (sz) begin
end else if (uz) begin
UNext = U;
UMNext = UM | K;
end else begin // If sp and sz are not true, then sn is
end else begin // If up and uz are not true, then un is
UNext = UM | K;
UMNext = UM;
end

12
pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh"
module fdivsqrtuotfc4(
input logic [3:0] s,
input logic [3:0] u,
input logic Sqrt,
input logic [`DIVb:0] U, UM,
input logic [`DIVb:0] C,
@ -47,19 +47,19 @@ module fdivsqrtuotfc4(
assign K3 = (C & ~(C << 2)); // 3K
always_comb begin
if (s[3]) begin
if (u[3]) begin
UNext = U | K2;
UMNext = U | K1;
end else if (s[2]) begin
end else if (u[2]) begin
UNext = U | K1;
UMNext = U;
end else if (s[1]) begin
end else if (u[1]) begin
UNext = UM | K3;
UMNext = UM | K2;
end else if (s[0]) begin
end else if (u[0]) begin
UNext = UM | K2;
UMNext = UM | K1;
end else begin // If sp and sn are not true, then sz is
end else begin // digit = 0
UNext = U;
UMNext = UM | K3;
end