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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-09-21 18:24:06 -05:00
commit f74d21e063
5 changed files with 16 additions and 15 deletions
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2
pipelined/regression/regression-wally
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@ -91,7 +91,7 @@ for test in tests32ic:
grepstr="All tests ran without failures")
configs.append(tc)
tests32i = ["wally32periph"]
tests32i = ["arch32i", "wally32periph"]
for test in tests32i:
tc = TestCase(
name=test,

2
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -92,7 +92,7 @@ module fdivsqrtiter(
logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper;
assign initCSqrt = 2'b11;
assign initCDiv2 = 2'b10;
assign initCDiv4 = 2'b10; // *** not sure why this works; seems like it should be 00 for initializing to -4
assign initCDiv4 = 2'b00; // *** not sure why this works; seems like it should be 00 for initializing to -4
assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2;
assign initC = {initCUpper, {`DIVb{1'b0}}};

12
pipelined/src/fpu/postproc/divshiftcalc.sv
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@ -42,11 +42,8 @@ module divshiftcalc(
);
logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt;
logic [`NE+1:0] DivDenormShift;
logic [`NORMSHIFTSZ-1:0] PreDivShiftIn;
logic [`DURLEN-1:0] DivEarlyTermShift = 0;
// is the result denromalized
// is the result denormalized
// if the exponent is 1 then the result needs to be normalized then the result is denormalizes
assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
@ -74,8 +71,5 @@ module divshiftcalc(
assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0;
assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift;
// *** explain why radix 4 division needs a left shift by 1
// *** can this shift be moved into the shiftcorrection logic?
assign PreDivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
assign DivShiftIn = PreDivShiftIn << (`RADIX==4 & ~Sqrt); // {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}};
assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}};
endmodule

4
pipelined/src/ieu/controller.sv
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@ -236,5 +236,7 @@ module controller(
// Stall pipeline at Fetch if a CSR Write or Fence is pending in the subsequent stages
assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FencePendingD | FencePendingE | FencePendingM;
assign StoreStallD = MemRWE[0] & ((|MemRWD) | (|AtomicD));
// the synchronous DTIM cannot read immediately after write
// a cache cannot read or write immediately after a write
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD));
endmodule

11
pipelined/testbench/testbench-fp.sv
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@ -104,6 +104,7 @@ module testbenchfp;
logic DivDone;
logic DivNegSticky;
logic [`NE+1:0] DivCalcExp;
logic divsqrtop;
///////////////////////////////////////////////////////////////////////////////////////////////
@ -878,12 +879,16 @@ always @(negedge clk) begin
// check if result is correct
// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
assign CheckNow = (DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
//assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
if(~(ResMatch & FlagMatch) & CheckNow) begin
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
errors += 1;
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("Error in %s", Tests[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
$stop;