Jarred Allen
85164c7a87
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 12:55:01 -04:00
Noah Boorstin
606295db2f
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-busybear.sv
2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1
Merge branch 'PPA' into main
...
Conflicts:
wally-pipelined/testbench/testbench-privileged.sv
2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b
removed minor bugs
2021-03-25 20:29:50 -04:00
ShreyaSanghai
da4086db79
Removed PCW and InstrW from ifu
2021-03-26 01:53:19 +05:30
Noah Boorstin
9eb1786fb1
busybear: quick fix to mem reading
...
also stop ignoring mcause at the start
2021-03-25 14:29:11 -04:00
Noah Boorstin
ed37e933e5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Noah Boorstin
355961f834
busybear: more progress
2021-03-23 14:49:30 -04:00
Noah Boorstin
0dae5401f3
busybear: more progress moving from instrf to instrrawd
2021-03-23 14:06:21 -04:00
Noah Boorstin
7fb2ebec50
busybear: ignore illegal instruction when starting
2021-03-23 13:28:56 -04:00
Noah Boorstin
3c131bb2bd
start migrating busybear over to InstrRawD/PCD
...
this breaks busybear for now
2021-03-22 23:45:04 -04:00
Noah Boorstin
1592332d41
Merge branch 'main' into cache
2021-03-22 23:28:30 -04:00
Noah Boorstin
43d23e3d9b
busybear: add better warning on illegal instruction
...
...also it seems that mret is being picked up as an illegal instruction??
2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0
busybear: temporarially force rf[5] correct after failure to read CSR
2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0
busybear: finally get the right error
2021-03-22 16:52:22 -04:00
Noah Boorstin
7350b9f18f
busybear: comment out some debug printing
2021-03-22 14:54:05 -04:00
Jarred Allen
507d8ed120
Merge branch 'main' into cache
2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1
regression: expect 200k instead of 100k busybear instrs
...
and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
Jarred Allen
bab0e3b90f
Change busybear testbench to reflect new location of InstrF
2021-03-20 18:20:27 -04:00
Shreya Sanghai
804407eab7
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Noah Boorstin
45ed2742cf
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Noah Boorstin
6d8bcfe6bf
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Noah Boorstin
f31d7a7f5c
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Noah Boorstin
87e2a9b920
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
1fc00d41c2
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Noah Boorstin
464c1de03d
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Noah Boorstin
923489fe16
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
932bc0ef85
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
0596d61a2a
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Noah Boorstin
4c7b185d90
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6
restored
2021-02-26 02:22:08 -08:00
kaveh pezeshki
251aa982eb
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043
busybear: preload bootram
...
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
2021-02-24 18:46:09 +00:00
kaveh pezeshki
06f73fe5fe
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8
busybear: add support for subwords in ram
...
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Noah Boorstin
5394d38e4a
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
Noah Boorstin
43f9abdbed
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
Noah Boorstin
84d856d1e5
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
dd3a5b74a1
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
Noah Boorstin
79fb83409f
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Noah Boorstin
01b1b1705d
Busybear: next week of updates
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- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
