mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-31 00:44:38 +00:00
01b1b1705d
- move parsed instructions out of git, to /courses/e190ax/busybear_boot - parsed first 1M instructions, and now parse from split GDB runs - now at about 230k instructions, can't progress further for now since atomic instructions aren't implemented yet
360 lines
12 KiB
Systemverilog
360 lines
12 KiB
Systemverilog
`include "wally-config.vh"
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module testbench_busybear();
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logic clk, reset;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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// instantiate device to be tested
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logic [`XLEN-1:0] PCF;
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logic [31:0] InstrF;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM = 0, SwIntM = 0; // from CLINT
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logic ExtIntM = 0; // not yet connected
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logic [`AHBW-1:0] HRDATA;
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logic HREADY, HRESP;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADY = 1;
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assign HRESP = 0;
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assign HRDATA = 0;
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// for now, seem to need these to be zero until we get a better idea
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assign InstrAccessFaultF = 0;
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assign DataAccessFaultM = 0;
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// instantiate processor and memories
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wallypipelinedhart dut(.*);
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// initialize test
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// read pc trace file
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integer data_file_PC, scan_file_PC;
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initial begin
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data_file_PC = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
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if (data_file_PC == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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end
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end
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integer data_file_PCW, scan_file_PCW;
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initial begin
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data_file_PCW = $fopen("/courses/e190ax/busybear_boot/parsedPC.txt", "r");
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if (data_file_PCW == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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end
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end
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// read register trace file
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integer data_file_rf, scan_file_rf;
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initial begin
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data_file_rf = $fopen("/courses/e190ax/busybear_boot/parsedRegs.txt", "r");
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if (data_file_rf == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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end
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end
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// read CSR trace file
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integer data_file_csr, scan_file_csr;
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initial begin
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data_file_csr = $fopen("/courses/e190ax/busybear_boot/parsedCSRs.txt", "r");
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if (data_file_csr == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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end
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end
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// read memreads trace file
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integer data_file_memR, scan_file_memR;
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initial begin
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data_file_memR = $fopen("/courses/e190ax/busybear_boot/parsedMemRead.txt", "r");
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if (data_file_memR == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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end
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end
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// read memwrite trace file
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integer data_file_memW, scan_file_memW;
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initial begin
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data_file_memW = $fopen("/courses/e190ax/busybear_boot/parsedMemWrite.txt", "r");
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if (data_file_memW == 0) begin
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$display("file couldn't be opened");
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#10; $stop;
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end
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end
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logic [63:0] pcExpected;
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logic [63:0] regExpected;
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integer regNumExpected;
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genvar i;
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generate
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for(i=1; i<32; i++) begin
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always @(dut.ieu.dp.regf.rf[i]) begin
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if ($time == 0) begin
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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#10; $stop;
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end
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end else begin
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scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (i != regNumExpected) begin
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$display("%t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected);
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end
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if (dut.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected);
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#10; $stop;
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end
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end
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end
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end
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endgenerate
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logic [`XLEN-1:0] readAdrExpected;
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// this might need to change
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always @(dut.MemRWM[1] or HADDR) begin
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if (dut.MemRWM[1]) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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#10; $stop;
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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#1;
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if (HADDR != readAdrExpected) begin
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$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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#10; $stop;
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end
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end
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end
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logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
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// this might need to change
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always @(HWDATA or HADDR or HSIZE) begin
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#1;
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if (HWRITE) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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#10; $stop;
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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if (writeDataExpected != HWDATA) begin
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$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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#10; $stop;
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end
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if (writeAdrExpected != HADDR) begin
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$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
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#10; $stop;
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end
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end
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end
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integer totalCSR = 0;
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logic [99:0] StartCSRexpected[63:0];
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string StartCSRname[99:0];
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initial begin
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while(1) begin
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scan_file_csr = $fscanf(data_file_csr, "%s\n", StartCSRname[totalCSR]);
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if(StartCSRname[totalCSR] == "---") begin
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break;
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end
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scan_file_csr = $fscanf(data_file_csr, "%x\n", StartCSRexpected[totalCSR]);
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totalCSR = totalCSR + 1;
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end
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end
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`define CHECK_CSR2(CSR, PATH) \
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string CSR; \
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logic [63:0] expected``CSR``; \
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//CSR checking \
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always @(``PATH``.``CSR``_REGW) begin \
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if ($time > 1) begin \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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if(CSR.icompare(`"CSR`")) begin \
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$display("%t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
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end \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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#10; $stop; \
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end \
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end else begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(`"CSR`")) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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#10; $stop; \
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end \
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end \
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end \
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end \
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end
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`define CHECK_CSR(CSR) \
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`CHECK_CSR2(CSR, dut.priv.csr)
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//`CHECK_CSR(FCSR)
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`CHECK_CSR(MCOUNTEREN)
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`CHECK_CSR(MEDELEG)
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`CHECK_CSR(MIDELEG)
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//`CHECK_CSR(MHARTID)
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`CHECK_CSR(MIE)
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`CHECK_CSR2(MISA, dut.priv.csr.genblk1.csrm)
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`CHECK_CSR2(MSCRATCH, dut.priv.csr.genblk1.csrm)
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`CHECK_CSR(MSTATUS)
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`CHECK_CSR(MTVEC)
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`CHECK_CSR2(SATP, dut.priv.csr.genblk1.csrs.genblk1)
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`CHECK_CSR(SCOUNTEREN)
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logic speculative;
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initial begin
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speculative = 0;
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speculative = 0;
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end
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logic [63:0] lastInstrF, lastPC, lastPC2;
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string PCtextW, PCtext2W;
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logic [31:0] InstrWExpected;
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logic [63:0] PCWExpected;
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always @(dut.ifu.PCW or dut.ieu.InstrValidW) begin
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if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin
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if($feof(data_file_PCW)) begin
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$display("no more PC data to read");
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#10; $stop;
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end
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scan_file_PCW = $fscanf(data_file_PCW, "%s\n", PCtextW);
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if (PCtextW != "ret" && PCtextW != "fence" && PCtextW != "nop" && PCtextW != "mret") begin
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scan_file_PC = $fscanf(data_file_PCW, "%s\n", PCtext2W);
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PCtextW = {PCtextW, " ", PCtext2W};
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end
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected);
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// then expected PC value
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
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if(dut.ifu.PCW != PCWExpected) begin
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$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected);
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#10; $stop;
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end
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//if(it.InstrW != InstrWExpected) begin
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// $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
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//end
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end
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end
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string PCtext, PCtext2;
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integer instrs;
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initial begin
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instrs = 0;
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end
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always @(PCF) begin
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lastInstrF = InstrF;
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lastPC <= PCF;
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lastPC2 <= lastPC;
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if (speculative && lastPC != pcExpected) begin
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speculative = (PCF != pcExpected);
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end
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else begin
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//if (~speculative) begin
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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#10; $stop;
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end
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
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if (PCtext != "ret" && PCtext != "fence" && PCtext != "nop" && PCtext != "mret") begin
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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PCtext = {PCtext, " ", PCtext2};
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end
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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if(InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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InstrF = 32'b0010011;
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$display("warning: NOPing out %s at PC=%0x", PCtext, PCF);
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end
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
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(instrs <= 100000 && instrs % 10000 == 0) || (instrs <= 1000000 && instrs % 100000 == 0)) begin
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$display("loaded %0d instructions", instrs);
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end
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instrs += 1;
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// are we at a branch/jump?
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casex (lastInstrF[31:0])
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32'b00000000001000000000000001110011, // URET
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32'b00010000001000000000000001110011, // SRET
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32'b00110000001000000000000001110011, // MRET
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
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32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
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32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
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32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
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speculative = 1;
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32'bXXXXXXXXXXXXXXXX1001000000000010: // C.EBREAK:
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speculative = 0; // tbh don't really know what should happen here
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32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
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32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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speculative = 1;
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default:
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speculative = 0;
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endcase
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//check things!
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if ((~speculative) && (PCF !== pcExpected)) begin
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$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
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#10; $stop;
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end
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end
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end
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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instrNameDecTB dec(InstrF, InstrFName);
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instrTrackerTB it(clk, reset, dut.ieu.dp.FlushE,
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dut.ifu.InstrD, dut.ifu.InstrE,
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dut.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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// generate clock to sequence tests
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always
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begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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//// check results
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//always @(negedge clk)
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// begin
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// if(MemWrite) begin
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// if(DataAdr === 84 & WriteData === 71) begin
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// $display("Simulation succeeded");
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// #10; $stop;
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// end else if (DataAdr !== 80) begin
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// $display("Simulation failed");
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// #10; $stop;
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// end
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// end
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// end
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endmodule
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