David Harris
7f7605737f
Cache code cleanup
2023-01-07 15:39:13 -08:00
David Harris
cdcee61aac
vclean working; started removing unused signals
2023-01-07 05:34:58 -08:00
David Harris
93bb8036be
Revert to 98b824
2022-12-22 23:58:14 -08:00
David Harris
567f76c2a5
Code cleanup
2022-12-22 10:04:50 -08:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
4a0e4aed99
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
b69aa39f30
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
1a24e7029f
Minor simplification of cacheway way selection muxes.
2022-12-09 16:42:05 -06:00
Ross Thompson
1a9c932157
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6
Removed commented code.
2022-12-05 17:21:56 -06:00
Ross Thompson
37551ecc43
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
2022-12-05 17:19:51 -06:00
Ross Thompson
dc31add951
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
3dea04e644
Moved selectedway mux into cacheway. It makes way more sense there.
2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae
Rename LineByteMux to FetchbufferbyteSel.
2022-12-04 01:00:04 -06:00
Ross Thompson
3442b04f9e
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
5025664cb0
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
Ross Thompson
cedb234013
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
b5718c9baa
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
e1dbe58632
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
0106777f02
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
42111db671
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
18e739befc
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
7f1ae039b0
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
David Harris
bc0c7d0cd8
Cleaned up SelBusWord
2022-08-25 11:18:13 -07:00
David Harris
3ba961d1a8
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
Ross Thompson
ebe4339953
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
2ba390adf4
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
413a9bf58b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-01 22:09:11 -05:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
3cd8404917
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Katherine Parry
1bd6351e1f
re-added FStore2 in Cache
2022-07-29 22:54:49 +00:00
Ross Thompson
40e7cda84a
Don't use this commit yet. Untested.
2022-07-24 15:40:52 -05:00
Ross Thompson
05484c4c05
signal name cleanup.
2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad
cache cleanup after removing replay on cpubusy.
2022-07-22 23:30:25 -05:00
Ross Thompson
abc79c6c8e
Possible improvement to cache which removes the cpu_busy states.
2022-07-22 23:20:37 -05:00
Ross Thompson
a79e5e11f6
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
