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207 lines
11 KiB
Systemverilog
207 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// cache (data cache)
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the L1 data cache
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//
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// Purpose: Storage for data and meta data.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, DCACHE) (
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input logic clk,
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input logic reset,
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input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
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input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
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// cpu side
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input logic [1:0] CacheRW, // [1] Read, [0] Write
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input logic [1:0] CacheAtomic, // Atomic operation
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input logic FlushCache, // Flush all dirty lines back to memory
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input logic InvalidateCache, // Clear all valid bits
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input logic [11:0] NextAdr, // Virtual address, but we only use the lower 12 bits.
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input logic [`PA_BITS-1:0] PAdr, // Physical address
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input logic [(WORDLEN-1)/8:0] ByteMask, // Which bytes to write (D$ only)
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input logic [WORDLEN-1:0] CacheWriteData, // Data to write to cache (D$ only)
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output logic CacheCommitted, // Cache has started bus operation that shouldn't be interrupted
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output logic CacheStall, // Cache stalls pipeline during multicycle operation
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output logic [WORDLEN-1:0] ReadDataWord, // Word read from cache (goes to CPU and bus)
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// to performance counters to cpu
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output logic CacheMiss, // Cache miss
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output logic CacheAccess, // Cache access
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// lsu control
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input logic SelHPTW, // Use PAdr from Hardware Page Table Walker rather than NextAdr
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// Bus fsm interface
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input logic CacheBusAck, // Bus operation completed
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input logic SelBusBeat, // Word in cache line comes from BeatCount
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input logic [LOGBWPL-1:0] BeatCount, // Beat in burst
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input logic [LINELEN-1:0] FetchBuffer, // Buffer long enough to hold entire cache line arriving from bus
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output logic [1:0] CacheBusRW, // [1] Read or [0] write bus
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output logic [`PA_BITS-1:0] CacheBusAdr // Address for bus access
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);
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// Cache parameters
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localparam LINEBYTELEN = LINELEN/8; // Line length in bytes
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localparam OFFSETLEN = $clog2(LINEBYTELEN); // Number of bits in offset field
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localparam SETLEN = $clog2(NUMLINES); // Number of set bits
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localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits
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localparam TAGLEN = `PA_BITS - SETTOP; // Number of tag bits
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localparam WORDSPERLINE = LINELEN/WORDLEN; // Number of words in cache line
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localparam FLUSHADRTHRESHOLD = NUMLINES - 1; // Used to determine when flush is complete
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localparam LOGLLENBYTES = $clog2(WORDLEN/8); // Number of bits to address a word
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localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN; // *** see if this is the same as WORDSPERLINE
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localparam LOGCWPL = $clog2(CACHEWORDSPERLINE); // ***
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logic SelAdr;
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logic [1:0] AdrSelMuxSel;
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logic [SETLEN-1:0] CAdr;
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logic [LINELEN-1:0] LineWriteData;
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logic ClearValid, ClearDirty, SetDirty, SetValid;
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logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] HitWay, ValidWay;
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logic CacheHit;
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logic [NUMWAYS-1:0] VictimWay, DirtyWay;
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logic LineDirty;
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logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] Tag;
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logic [SETLEN-1:0] FlushAdr, NextFlushAdr, FlushAdrP1;
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logic FlushAdrCntEn, FlushCntRst;
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logic FlushAdrFlag, FlushWayFlag;
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logic [NUMWAYS-1:0] FlushWay, NextFlushWay;
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logic FlushWayCntEn;
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logic SelWriteback;
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logic LRUWriteEn;
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logic SelFlush;
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logic ResetOrFlushCntRst;
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logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache;
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logic SelFetchBuffer;
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logic CacheEn;
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logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded;
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logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, FetchBufferByteSel;
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logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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genvar index;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Read Path
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Choose read address (CAdr). Normally use NextAdr, but use PAdr during stalls
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// and FlushAdr when handling D$ flushes
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// The icache must update to the newest PCNextF on flush as it is probably a trap. Trap
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// sets PCNextF to XTVEC and the icache must start reading the instruction.
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assign AdrSelMuxSel = {SelFlush, ((SelAdr | SelHPTW) & ~((DCACHE == 0) & FlushStage))};
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mux3 #(SETLEN) AdrSelMux(.d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
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.s(AdrSelMuxSel), .y(CAdr));
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .CacheEn, .CAdr, .PAdr, .LineWriteData, .LineByteMask,
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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// Select victim way for associative caches
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if(NUMWAYS > 1) begin:vict
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cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
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.clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage),
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.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
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end else
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assign VictimWay = 1'b1; // one hot.
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assign CacheHit = |HitWay;
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assign LineDirty = |DirtyWay;
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// ReadDataLineWay is a 2d array of cache line len by number of ways.
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// Need to OR together each way in a bitwise manner.
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// Final part of the AO Mux. First is the AND in the cacheway.
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or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLineCache));
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or_rows #(NUMWAYS, TAGLEN) TagAOMux(.a(TagWay), .y(Tag));
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// Data cache needs to choose word offset from PAdr or BeatCount to writeback dirty lines
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if(DCACHE)
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mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
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.d1(BeatCount), .s(SelBusBeat),
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.y(WordOffsetAddr));
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else
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assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
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// Bypass cache array to save a cycle when finishing a load miss
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mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelFetchBuffer, ReadDataLine);
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// Select word from cache line
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subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread(
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.PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
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// Bus address for fetch, writeback, or flush writeback
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mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
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.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Adjust byte mask from word to cache line
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onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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for(index = 0; index < 2**LOGCWPL; index++) begin
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assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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end
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assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
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assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
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// Merge write data into fetched cache line for store miss
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for(index = 0; index < LINELEN/8; index++) begin
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mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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.d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Flush logic
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Flush address (line number)
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assign ResetOrFlushCntRst = reset | FlushCntRst;
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flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);
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mux2 #(SETLEN) FlushAdrMux(NextFlushAdr, FlushAdrP1, FlushAdrCntEn, FlushAdr);
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assign FlushAdrP1 = NextFlushAdr + 1'b1;
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assign FlushAdrFlag = (NextFlushAdr == FLUSHADRTHRESHOLD[SETLEN-1:0]);
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// Flush way
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flopenl #(NUMWAYS) FlushWayReg(clk, ResetOrFlushCntRst, FlushWayCntEn, {{NUMWAYS-1{1'b0}}, 1'b1}, NextFlushWay, FlushWay);
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if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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else assign NextFlushWay = FlushWay[NUMWAYS-1];
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.FlushStage, .CacheRW, .CacheAtomic, .Stall,
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.CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
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.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
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.InvalidateCache, .CacheEn, .LRUWriteEn);
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endmodule
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