Github_Repos/cvw
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2156 Commits

Author SHA1 Message Date
David Harris
b89fe9989e Renamed DCACHE to DCACHE_SUPPORTED and ICACHE to ICACHE_SUPPORTED 2023-01-28 18:52:00 -08:00
David Harris
fa3643a064 Renamed BUS to BUS_SUPPORTED 2023-01-28 18:35:53 -08:00
David Harris
8a96dcf0ae Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED 2023-01-28 18:17:42 -08:00
David Harris
c73fe4041e Fixed typo in ram2p1r1wbe_1024x69 and renamed for consistency 2023-01-28 18:07:33 -08:00
David Harris
e27ab1a052 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 17:55:08 -08:00
James Stine
5a0d8aed23 Modified changes as follows 
* Add docs directory for Docker including Dockerfile
* Change to synthesis script to include fpu stuff
* Add wrappers for IP (may need some cleanup but will cleanup shortly)
 2023-01-28 19:33:00 -06:00
Ross Thompson
6945eaf045 Fixed bug with the new csr. 2023-01-28 17:56:56 -06:00
Ross Thompson
684a7214cb Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
Ross Thompson
3ddf95ac6e Found an issue where the btb was not forwarding the valid bit! 2023-01-28 17:00:50 -06:00
Ross Thompson
b52990e2ce Possible workign instruction class prediction repair. 2023-01-28 16:42:19 -06:00
Ross Thompson
3f25123c63 Possible fix for speculative gshare. 2023-01-28 16:14:19 -06:00
David Harris
ed1aaa6c8f Comment cleanup in subcachelineread 2023-01-28 11:00:05 -08:00
David Harris
1b0b9314c4 removed unused memory model 2023-01-28 10:58:36 -08:00
David Harris
6c59c21a26 Updated cvw to be consistent with configs 2023-01-28 10:58:02 -08:00
David Harris
1041775be4 Removed DEISGN_COMPILER configuration paramter 2023-01-28 10:51:39 -08:00
David Harris
eeaa5d9982 Removed unneeded lint directive from core 2023-01-27 15:48:30 -08:00
David Harris
aee984ca69 Use CVW configuration in top-level 2023-01-27 15:47:36 -08:00
David Harris
c2ce2947f9 Removed unused BMU, added CVW configuration 2023-01-27 15:47:15 -08:00
David Harris
5547179a3c Added missing PLIC_GPIO_ID to two config files 2023-01-27 15:23:32 -08:00
David Harris
848ccd8b90 Fixed license header for config files to SolderPad 2023-01-27 15:17:17 -08:00
Ross Thompson
a953954909 Clarified gshare bp. 2023-01-27 16:40:20 -06:00
David Harris
a99fc74976 Removed integer from localparams 2023-01-27 14:40:06 -08:00
David Harris
717cb4e6c5 Removed int/integer from parameters) 2023-01-27 14:27:04 -08:00
Ross Thompson
121fbd9646 Removed pessimistic x propagation issue for wally32priv test in the branch predictor. 2023-01-27 15:28:31 -06:00
Ross Thompson
cf49c7ddc1 Found issue with branch predictor. 2023-01-27 13:13:55 -06:00
David Harris
44c7102026 Renamed ram2p1rw1be to match modeule name 2023-01-27 09:54:50 -08:00
Ross Thompson
6c86c0389c Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction. 2023-01-27 11:34:45 -06:00
David Harris
4744996282 Removed suggestion about make allclean 2023-01-27 05:57:05 -08:00
David Harris
4f7e1b9423 Fixed typo in bpred preventing compiling 2023-01-27 05:55:53 -08:00
David Harris
e682b8d0d4 renamed brpred to bpred 2023-01-27 05:55:31 -08:00
David Harris
3986e84179 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-26 14:52:25 -08:00
Ross Thompson
bbb47fc943 Changed the performance counters to track different data. 
Now rather than tracking jump(r) we track jump(r) and taken branches.
 2023-01-26 13:21:28 -06:00
Ross Thompson
e0ca23cdd6 Fixed another bug with the compressed instruction class decode. 2023-01-26 12:19:33 -06:00
Ross Thompson
3652673487 Fixed compressed branch class decode. 2023-01-26 11:07:47 -06:00
Ross Thompson
2ee6ffe74b Improved no class prediction mode. 2023-01-26 10:54:43 -06:00
Ross Thompson
29d4cd7ffa Modified the RAS to correctly repair itself. 2023-01-25 23:33:03 -06:00
Ross Thompson
43d4ac1c7b Intermediate commit. Passes regression tests, but RAS is not correct. 2023-01-25 19:39:18 -06:00
Ross Thompson
4e858199e5 Fixed typos. 2023-01-25 18:51:09 -06:00
Ross Thompson
e1d0be5c61 RAS is now compliant with our header and documentation guide. 2023-01-25 17:18:07 -06:00
Ross Thompson
0b9f787635 Improved RAS again. 2023-01-25 17:10:52 -06:00
Ross Thompson
172c40d44b Improved RAS. 2023-01-25 17:06:25 -06:00
Ross Thompson
56aa798d5c More branch predictor improvements. 2023-01-25 16:03:02 -06:00
Ross Thompson
3d285312f0 Cleaned up branch predictor. 2023-01-25 15:29:55 -06:00
Ross Thompson
bb89bf82bf Fixed subtle bug in btb. 2023-01-25 15:16:53 -06:00
Ross Thompson
d4004c2c22 Added logic to forward btb prediction results. 2023-01-25 13:02:20 -06:00
Ross Thompson
541524a754 More btb cleanup. 2023-01-25 12:14:18 -06:00
Ross Thompson
85e015d61e Found minor bug in gshare. 2023-01-25 12:08:54 -06:00
Ross Thompson
a0bca35b50 BTB cleanup. 2023-01-25 12:05:13 -06:00
Ross Thompson
5030a56f57 Optomized gshare. 2023-01-25 11:41:16 -06:00
Ross Thompson
a5bd78a622 Renamed file missed from last commit. 2023-01-25 10:17:43 -06:00
Ross Thompson
1e7fda6410 Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. 
Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv
 2023-01-25 10:14:30 -06:00
Ross Thompson
42553d1d94 Removed old versions of gshare. 2023-01-24 17:26:54 -06:00
Ross Thompson
0d7653f1c7 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
3d07f7a3a2 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
7ae6b1868e Partial BTB cleanup. 2023-01-24 16:12:35 -06:00
Ross Thompson
879cb77b90 Moved branch predictor files into separate sub-directory. 2023-01-24 16:00:27 -06:00
David Harris
7d015151bb Merge remote-tracking branch 'upstream/main' into dev 2023-01-24 09:40:07 -08:00
David Harris
0e5ea5f51d bpred input spacing cleanup 2023-01-24 06:14:31 -08:00
David Harris
30b085911a bpred tab cleanup 2023-01-24 05:42:34 -08:00
Ross Thompson
89698a929e Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
d495d7b04d Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
45094fc7bb Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e1c121fe0d Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
bb11de0f4c Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
David Harris
678a879415 formatting 2023-01-23 10:54:06 -08:00
David Harris
b6b67516eb Repo cleanup 2023-01-23 10:37:33 -08:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
c2f7f7324d test 2023-01-20 15:23:38 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
1933ea39fa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
0f68fccf82 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
3d71d0196c Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b1f3bd566c Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597 Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946 Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7 Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
95de716a17 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
032332ebae renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
eb19b1b499 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
6f3b8680d5 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 09:41:18 -06:00
Ross Thompson
63dbebcb5a Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
91bd55d9ba ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
30935fd2b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
78e8598ec8 Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
aed6f79d1e Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
ad3b528b5d Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
264362ce17 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
a1b25e1039 RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
75391f4b56 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1 Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
eroom1966
43d5769bd9 update 2023-01-19 13:29:46 +00:00
Ross Thompson
0bbf6e4ae2 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00