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Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction.

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This commit is contained in:
Ross Thompson 2023-01-27 11:34:45 -06:00
parent bbb47fc943
commit 6c86c0389c
3 changed files with 42 additions and 9 deletions
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30
pipelined/regression/wave.do
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@ -588,8 +588,34 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0}
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0}
quietly wave cursor active 5
configure wave -namecolwidth 250
configure wave -valuecolwidth 194
@ -605,4 +631,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {48955732 ns} {48955990 ns}
WaveRestoreZoom {2195 ns} {2479 ns}

2
pipelined/src/ifu/brpred/bpred.sv
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@ -28,7 +28,7 @@
`include "wally-config.vh"
`define INSTR_CLASS_PRED 0
`define INSTR_CLASS_PRED 1
module bpred (
input logic clk, reset,

19
pipelined/src/ifu/brpred/speculativegshare.sv
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@ -51,7 +51,8 @@ module speculativegshare
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
logic [k-1:0] GHRF;
logic [k-1:0] GHRF, OldGHRF;
logic OldGHRExtraF;
logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
logic [k-1:0] GHRNextF;
logic [k:-1] GHRNextD, OldGHRD;
@ -105,17 +106,23 @@ module speculativegshare
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
// GHR pipeline
assign GHRNextF = FlushD ? GHRNextD[k:1] :
assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) :
BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
GHRF;
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF);
flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right
WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit
OldGHRF[k:0];
assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
OldGHRD[k:0];
//assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
// WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
// OldGHRD[k:0];
assign GHRD = OldGHRD[k:0];
assign GHRNextE = FlushE ? GHRNextM : GHRD;
flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);