David Harris
7e3f75a35d
Formatting cache.sv
2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20
sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f
Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
2022-05-03 03:45:41 -07:00
David Harris
7268ff1fd4
Changed loop variable in CLINT because of error only seen on VLSI
2022-05-03 10:10:28 +00:00
David Harris
6e8b27de17
Added torture.tv test vectors
2022-04-27 13:08:36 +00:00
David Harris
ffd4713fd1
Checked in torture.tv
2022-04-27 13:06:24 +00:00
David Harris
9042844b38
Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv
2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
8ad920fcb3
fixed initial value, timing on fs bits changing after floating point instruction
2022-04-25 19:17:29 +00:00
David Harris
cf1fde62fb
Restored MPRV behavior per spec
2022-04-25 14:52:18 +00:00
David Harris
0ede295e88
Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
2022-04-25 14:49:00 +00:00
David Harris
851d5e8c5e
Added MTINST hardwired to 0, and added timeout of U-mode WFI
2022-04-24 20:00:02 +00:00
David Harris
16ad1e0cab
Fixed InstrMisalignedFaultM mtval
2022-04-24 17:31:30 +00:00
David Harris
f1ddbb169c
Improved priority order and mtval of traps to match spec
2022-04-24 17:24:45 +00:00
David Harris
03f84bf11c
Extended sim time to fully boot Linux. Added comments to hazard unit
2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
7bc6943527
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
bbracker
afc38abe08
change how tristate I/O is spoofed in GPIO loopback test
2022-04-21 10:31:16 -07:00
David Harris
5c607f2b6b
Simplified profile for UART boot; added warnings on UART Rx errors
2022-04-21 04:54:45 +00:00
David Harris
1f7a95637a
Added baby torture tests
2022-04-19 15:13:06 +00:00
David Harris
a8ad7be246
Fixed WFI decoding in IFU
2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
1ba328324b
Added GPIO loopback to let outputs cause interrupts
2022-04-18 07:22:49 +00:00
Shreya Sanghai
fd3920b217
replaced k with bpred size
2022-04-18 04:21:03 +00:00
David Harris
462158ea92
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
4a7effaf9e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-04-18 01:30:11 +00:00
David Harris
2882460c94
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
Ross Thompson
c045e3afd8
Added back the instret counter to ILA.
2022-04-17 18:44:07 -05:00
David Harris
2819a1c305
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
David Harris
812b56acc6
Prefix comparator cleanup
2022-04-17 21:53:11 +00:00
David Harris
de5b61291f
Experiments with prefix comparator; minor fixes in WFI and testbench warnings
2022-04-17 21:43:12 +00:00
Ross Thompson
059c04e2a8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de
Increased uart baud rate to 230400.
...
Added uart signals to debugger.
2022-04-17 15:23:39 -05:00
David Harris
2436534687
First implementation of WFI timeout wait
2022-04-17 17:20:35 +00:00
David Harris
83d283354c
Added comments in fcvt
2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d
Simplified SLT logic
2022-04-17 16:49:51 +00:00
Ross Thompson
16b3c64234
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
David Harris
855d68afde
WFI should set EPC to PC+4
2022-04-14 17:05:22 +00:00
Ross Thompson
7d0462dc59
UART and clock speed changes to support 30Mhz.
2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
2294cbc1c6
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
2022-04-07 16:56:28 -05:00
Katherine Parry
c307cff503
fixed errors and warnings in rv32e
2022-04-07 17:21:20 +00:00
Ross Thompson
9517fe9faf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-05 15:42:07 -05:00
Ross Thompson
7abde2b566
Increazed fpga clock speed to 35Mhz.
...
linux boot is much faster.
2022-04-05 15:09:49 -05:00
Katherine Parry
20885f4dea
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
Ross Thompson
0ed34b8e63
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e
Constraint changes for 40Mhz wally.
2022-04-04 10:50:48 -05:00
Ross Thompson
0806d1a134
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
2022-04-04 10:38:37 -05:00
Ross Thompson
d83db2cde5
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
2022-04-04 09:57:26 -05:00
Ross Thompson
fd9a33e453
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-03 17:56:55 -05:00
