Commit Graph

17 Commits

Author SHA1 Message Date
David Harris
1a6fb2fad9 Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
79c1395967 merging changes 2021-10-26 08:34:36 -07:00
David Harris
44de52a05a Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
09b3549efd Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
87aaec3b6c Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
Ross Thompson
d8d414665c fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
Ross Thompson
230c794edd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Refixed some bit width issues in the icache.
2021-09-09 12:44:02 -05:00
Ross Thompson
90f2821bea fixed some lint bugs. 2021-09-09 12:38:57 -05:00
David Harris
cb624fe679 Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
Ross Thompson
cbb47956cb Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
b5eba44417 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
83cc0266b2 Rename of DCacheMem to cacheway.
simplified dcache names.
2021-08-25 13:33:15 -05:00