98 Commits

Author	SHA1	Message	Date
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
Thomas Fleming	8c410b6fbe	Install dtlb in dmem	2021-03-04 03:30:06 -05:00
Thomas Fleming	1a2db17ee5	Install tlb into ifu	2021-03-04 03:11:34 -05:00
Thomas Fleming	ab6ae6d3f1	Merge branch 'tlb_toy' into main	2021-03-04 02:41:11 -05:00
Thomas Fleming	7a9f866120	Move tlb into mmu directory	2021-03-04 02:39:08 -05:00
Teo Ene	b15ef47d24	Fix to 32-bit option of commit 2d40898158	2021-03-04 01:33:34 -06:00
Thomas Fleming	d821a1dbfa	Merge branch 'main' into tlb_toy	2021-03-04 01:18:04 -05:00
Thomas Fleming	c03b540956	Generalize tlb module ... - number of tlb entries is now parameterized - tlb now supports rv64i	2021-03-04 01:13:31 -05:00
David Harris	23a1cf63b3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-01 00:09:55 -05:00
David Harris	6f4e8b723e	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
Teo Ene	2d40898158	Properly implemented the fix from commit 5fee65231e	2021-02-28 22:22:04 -06:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	225102047a	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	1b61d78ac2	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
David Harris	bad180fc15	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-25 15:49:38 -05:00
David Harris	f57096a5d2	Restored to working multiplier after Lab 2	2021-02-25 15:32:43 -05:00
Brett Mathis	b0a5052bcf	FPU Assembly tests	2021-02-25 14:32:36 -06:00
Teo Ene	a35fdac75b	Fixed previous commit	2021-02-25 11:24:44 -06:00
Teo Ene	5fee65231e	Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.	2021-02-25 11:23:01 -06:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Katherine Parry	07641203ee	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-23 20:21:53 +00:00
Katherine Parry	906ec30339	inital FMA push	2021-02-23 20:19:12 +00:00
David Harris	7737b0f709	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	f372e2b8e8	Debugging Bus interface	2021-02-22 13:48:30 -05:00
Thomas Fleming	ca51e7ca1c	Create simple TLB ... This TLB is just a demonstration and is not currently instantiated by the IFU or DFU.	2021-02-18 18:06:09 -05:00
David Harris	87ad559a90	Updated creation date of mul	2021-02-18 08:13:08 -05:00
David Harris	fe7299c155	Resotred part of multiplier for lab 2	2021-02-17 16:14:04 -05:00
David Harris	492ec0ee78	Removed multiplier for lab 2	2021-02-17 16:06:16 -05:00
David Harris	e8d3c7d9e7	Multiplier tweaks	2021-02-17 16:00:27 -05:00
David Harris	e64e8afb7f	Started to integrate OSU divider	2021-02-17 15:38:44 -05:00
David Harris	a7dd20b388	Multiply instructions working	2021-02-17 15:29:20 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
bbracker	deb7780897	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	b121b90b28	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	74bc4c0444	Fixed lw by delaying read value by one cycle	2021-02-07 23:28:21 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
David Harris	2a80bcf543	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
David Harris	756352f129	Minor tweaks	2021-02-02 19:44:37 -05:00
Noah Boorstin	b5f474d9f5	same thing but do that right this time	2021-02-02 21:47:15 +00:00
Noah Boorstin	6dd5c42d55	change undefined syntax in extend.sv ... don't need verilator execption anymore	2021-02-02 21:39:20 +00:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	9f9c3bcece	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	616830a3f0	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	229bde5953	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00