Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
3b8bdc7b2d
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
David Harris
106982e493
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
88b2d9e687
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce
IEU cleanup
2021-10-23 11:13:28 -07:00
David Harris
5235e61d9e
Lint cleanup
2021-10-23 09:06:21 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
d8d414665c
fixed issues with dc shell not liking modules with parameters without default values.
2021-10-18 17:24:15 -05:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
kipmacsaigoren
8e35701103
Merging new changes into the old one's I've made in the OKstate servers
2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
3623dfa51e
removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
2021-10-08 15:33:18 -07:00
Ross Thompson
232d4a554f
Have program which checks for sdc init and issues read, but read done is
...
not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
4256ef82b1
SDC to ABHLite interface partially done.
...
Added SDC to adrdec and uncore.
2021-09-24 10:45:09 -05:00
Kip Macsai-Goren
f1981a1267
more input changes on prioirty thermometer. passes lint
2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2
added new fun ways of putting inputs into the priority thermometer
2021-09-17 12:00:38 -05:00
kipmacsaigoren
437f2d5814
changed priority circuits for synthesis and light cleanup
2021-09-15 12:24:24 -05:00
David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
James E. Stine
5bc3569b0e
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
a99b5f648b
partial dcache reorg.
2021-08-25 12:42:05 -05:00
Ross Thompson
66ad510abf
Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.
2021-08-16 10:02:29 -05:00
Ross Thompson
ce29d0f00f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-26 11:55:00 -05:00
Ross Thompson
0291d987da
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
kipmacsaigoren
3bb6c8b32f
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5306d42bfe
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
1e88784bd4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
511c36fb1b
Improved address bus names and usages in the walker, dcache, and tlbs.
...
Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Kip Macsai-Goren
e59490d032
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Kip Macsai-Goren
c1c564d54c
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
6ccbdc372d
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
f22b6e7397
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
David Harris
e31d2ef9f5
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
40c5d3ced7
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
David Harris
a5a7be3e03
Removed EndWalk signal and simplified TLBMissReg
2021-07-18 03:26:43 -04:00
David Harris
f21582906f
Pushing HPTWPAdrM flop into LSUArb
2021-07-17 19:39:18 -04:00
David Harris
989bb7c01b
Simplified VPN case statement
2021-07-17 19:34:01 -04:00
David Harris
25450bd7c1
Finished HPTW TranslationPAdr simlification
2021-07-17 19:27:24 -04:00
David Harris
217bf37668
Further TranslationVAdr simplification
2021-07-17 19:24:37 -04:00
David Harris
d8397b5e8b
Continued Translation Address Cleanup of TranslationPAdrMux
2021-07-17 19:16:56 -04:00
David Harris
6f73844427
Continued Translation Address Cleanup
2021-07-17 19:09:13 -04:00
David Harris
2e2e948023
Refining address interface between HPTW and LSU
2021-07-17 19:02:18 -04:00
David Harris
12cfe91362
Fixed bad register in I-FSD-01 Imperas test.
2021-07-17 17:08:07 -04:00
David Harris
777e983c19
Finished removing PageTableEntry redundant signals from hptw
2021-07-17 15:50:52 -04:00
David Harris
d6b8a5e595
hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE
2021-07-17 14:48:44 -04:00
David Harris
ef03ec275c
hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states
2021-07-17 14:36:27 -04:00
David Harris
d19679f213
hptw: Eliminated A and D bit faults while walking page table, per spec
2021-07-17 14:29:20 -04:00
