Jordan Carlin
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a4967138b6
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Merge pull request #875 from ross144/main
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2024-07-11 18:05:14 -07:00 |
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Rose Thompson
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82bd9ca200
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-11 11:32:12 -05:00 |
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Rose Thompson
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8f52e4ae42
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Merge pull request #878 from JacobPease/main
Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.
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2024-07-11 11:25:24 -05:00 |
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Jacob Pease
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1a2607c3d9
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Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.
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2024-07-11 10:53:18 -05:00 |
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Ross Thompson
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c72f0fd504
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Added csr comparison.
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2024-07-11 10:49:06 -05:00 |
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Ross Thompson
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abf9da01ab
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code cleanup.
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2024-07-11 10:41:34 -05:00 |
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Ross Thompson
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f0096f5a43
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Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
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2024-07-10 15:10:37 -05:00 |
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Ross Thompson
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e6dc962d11
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Yay! the trigger is correctly working now!
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2024-07-10 12:05:10 -05:00 |
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Ross Thompson
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cf986b5fb8
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Really close to having the trigger in module work.
Can trigger on the data of the correct frame, but trigger in is still not
working.
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2024-07-09 19:04:51 -05:00 |
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Ross Thompson
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6734685333
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Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
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2024-07-09 19:04:18 -05:00 |
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Ross Thompson
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e0a1f0e39f
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Really close now.
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2024-07-09 14:21:43 -05:00 |
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Ross Thompson
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e488ee7225
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Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger.
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2024-07-09 14:16:13 -05:00 |
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Ross Thompson
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fd170a6583
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Getting closer.
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2024-07-09 14:09:56 -05:00 |
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Ross Thompson
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bf69a2e1cd
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Updated to use the newest imperasDV.
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2024-07-09 12:30:18 -05:00 |
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Rose Thompson
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f83e6cf771
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Fixed issue #874.
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2024-07-08 14:48:52 -05:00 |
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Jordan Carlin
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bea95c7d54
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Refactor section headers
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2024-07-08 07:21:08 -07:00 |
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Jordan Carlin
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70a65e2d6b
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Cleanup
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2024-07-08 06:50:29 -07:00 |
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Jordan Carlin
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09a061b580
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Merge remote-tracking branch 'upstream/main' into installation
Fix derivgen.pl shebang conflict
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2024-07-08 06:46:41 -07:00 |
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Rose Thompson
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15b23ceb4d
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Merge pull request #866 from davidharrishmc/dev
First version of iterelf running; removed directory support from wsim
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2024-07-07 10:27:22 -05:00 |
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David Harris
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9098a55ea3
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Fixed lint error in imperas derived config
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2024-07-06 05:36:12 -07:00 |
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David Harris
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bcbe9eec81
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Added lockstep simulations for coverage, wally-riscv-arch-test, buildroot boot to nightly / buildroot regression
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2024-07-05 22:13:34 -07:00 |
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David Harris
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84c687080d
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-07-05 21:42:26 -07:00 |
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David Harris
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9f5e7b8653
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Merge pull request #851 from kevindkim723/intdivb
Reduce Bit widths for IDIV on FPU
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2024-07-05 21:42:19 -07:00 |
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David Harris
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02a7a1696b
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git ignore
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2024-07-05 21:35:10 -07:00 |
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David Harris
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ffb248dc65
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Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit
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2024-07-05 21:32:57 -07:00 |
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David Harris
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9279b2d56a
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Added imperas configuration for Lee
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2024-07-05 09:13:18 -07:00 |
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David Harris
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ced8038343
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Defined memory to be inaccessible by default
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2024-07-05 08:34:28 -07:00 |
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Jordan Carlin
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6d46549ee3
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Fix setup.csh typo
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2024-07-04 13:45:24 -07:00 |
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Jordan Carlin
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47501b9ef4
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Add comments to site-setup for new gcc
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2024-07-04 13:44:50 -07:00 |
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David Harris
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604f9d3a45
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Fixed imperas.ic prefix for vcs
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2024-07-04 12:31:00 -07:00 |
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David Harris
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873bd61296
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Fixed perl path in derivgen
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2024-07-04 12:30:11 -07:00 |
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David Harris
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12717a65f2
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Fixed location of imperas.ic with new misa_B_Zba_Zbb_Zbs
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2024-07-04 12:29:59 -07:00 |
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David Harris
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775930ae4f
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Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test
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2024-07-04 07:36:56 -07:00 |
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Jordan Carlin
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a7b78e6773
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Fix perl shebang lines
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2024-07-04 01:48:20 -07:00 |
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Jordan Carlin
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985d9b4edc
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Update run_vcs shebang after merge
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2024-07-03 23:47:26 -07:00 |
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Jordan Carlin
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0459c68615
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Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
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2024-07-03 23:44:25 -07:00 |
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Jordan Carlin
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c7d556a7ed
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Update installation script comments
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2024-07-03 23:42:31 -07:00 |
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Jordan Carlin
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090a4f9544
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Add error messages
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2024-07-03 22:26:10 -07:00 |
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Jordan Carlin
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eaac8e9b6a
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Speed up qemu clone with multiple submodules in parallel
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2024-07-03 22:14:17 -07:00 |
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Jordan Carlin
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a30d4b29df
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Additional shebang updates
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2024-07-03 21:34:48 -07:00 |
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Jordan Carlin
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7419689359
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Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
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2024-07-03 20:42:55 -07:00 |
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Jordan Carlin
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f9e865e537
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Update README with new installation flow and other general cleanup
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2024-07-03 19:51:52 -07:00 |
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David Harris
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8645441d00
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Testbench automatically creates memfile, label, addr files if they are out of date or missing
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2024-07-03 16:52:16 -07:00 |
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David Harris
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9b120bb3aa
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fix timeout in iterelf
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2024-07-03 16:34:14 -07:00 |
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David Harris
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4528b4ee2a
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Fix wsim to use absolute path for ELF
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2024-07-03 15:10:02 -07:00 |
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David Harris
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f7797d6092
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First version of iterelf running; removed directory support from wsim
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2024-07-03 14:54:46 -07:00 |
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Rose Thompson
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764f46a174
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Merge pull request #865 from davidharrishmc/dev
EBU HPROT based on instruction/data, sim progress
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2024-07-03 08:04:43 -07:00 |
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David Harris
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af4403342f
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renamed run_vcs.py to run_vcs, added instr/data in ebu
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2024-07-03 08:02:38 -07:00 |
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David Harris
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a2fb6a21c5
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Removed testbench-imperas now that wsim supports lockstep and single ELF files
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2024-07-03 06:25:32 -07:00 |
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Rose Thompson
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dc2b596425
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Merge pull request #863 from davidharrishmc/dev
Regression runs buildroot to login prompt; VCS lockstep progress
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2024-07-03 05:58:40 -07:00 |
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