David Harris
2a7e77d2b1
Do file for riscvsingle
2022-01-10 16:26:18 +00:00
David Harris
6587bd6944
Added fulladder example files
2022-01-10 16:15:05 +00:00
David Harris
4cae11ad28
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
50c17f2a03
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
467aac8463
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
e01c8bc5f6
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
3109fa1383
Fixed wavefile.
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Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
Ross Thompson
73f7d36529
Added additional fsm to ILA.
2022-01-09 17:10:57 -06:00
Ross Thompson
c8689dc6ce
Possible fix for the TrapM DTLBMiss suppression.
2022-01-09 14:22:14 -06:00
Kip Macsai-Goren
53f3a6dbab
comment cleanup
2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
9412a5ff2d
updated PMA tests, everything passes except successful writes to protected regions.
2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
a22dc4d163
changed test case types to lookup table instead of beq's
2022-01-09 16:56:37 +00:00
David Harris
89ee6c778e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
David Harris
80c87d16a9
Fixed RISCV path in coremark Makefile
2022-01-09 14:39:22 +00:00
Ross Thompson
2846118261
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
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This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-08 20:49:45 -06:00
Ross Thompson
b856301ecf
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-08 17:21:27 -06:00
Ross Thompson
9c3dffb714
Hack "fix" to prevent interrupt from occuring during an integer divide.
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This is not the desired solution but will allow continued debuging of linux.
2022-01-08 14:21:58 -06:00
Ross Thompson
09d605ac6a
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
88d5edaf13
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
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only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
453a794f86
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
913a78323c
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
6c0cd5ef20
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
8481c93e1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
de3bbd3fe0
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
261882bf78
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
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assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
2df92af488
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
27c1d73cb1
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
5402b55c44
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
0438975e27
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
0c8d556311
Tests cleanup:
2022-01-06 23:07:22 +00:00
David Harris
6fafabbfad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
53637049b7
Makefile make allclean
2022-01-06 23:04:30 +00:00
David Harris
ae64b859c3
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
631d05dcdc
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e0740034f0
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
3bfe23bc75
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
f23965d47f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 21:45:20 +00:00
David Harris
770780e394
Floating point test cleanup
2022-01-06 21:45:16 +00:00
Ross Thompson
6117c43028
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 15:18:27 -06:00
Ross Thompson
3625fc3bed
Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
2022-01-06 15:18:18 -06:00
David Harris
a5a89e58a8
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
eff9cec415
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
aca26de498
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
Ross Thompson
6edd4c5759
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 11:56:23 -06:00
Ross Thompson
c19b910f6e
Updated fpga ILA constraints to match the new changes to the rtl.
2022-01-06 11:56:09 -06:00
