James E. Stine
760291d6cc
On some Ubuntu boxes, the path for Wally interferes with other tools. Prepending Wally path to make sure there are no conflicts.
2024-04-09 09:00:45 -05:00
Rose Thompson
e53e12ad5c
Merge pull request #719 from Shreesh-Kulkarni/patch-4
...
Modified coremark_sweep.py to tabulate both 32 and 64-bit configurations.
2024-04-08 13:59:31 -05:00
Shreesh Kulkarni
18b367e0b0
updated date of file modification
2024-04-08 22:58:32 +05:30
Shreesh Kulkarni
dd3d36d1a7
Modified coremark_sweep.py to tabulate both 32 and 64-bit configurations.
...
Modified the script to tabulate 64-bit RISC-V configurations as well.
2024-04-08 22:56:32 +05:30
David Harris
3e9ef8bd92
Merge pull request #717 from jordancarlin/main
...
Update tool-chain-install to only build Sail c emulator
2024-04-08 08:18:25 -07:00
Jordan Carlin
e0312bd3af
Update tool-chain-install to only build Sail c emulator
...
Wally only uses the c emulator, so there is no reason to have it build the other models (like ocaml).
When only the c emulator is used it is also able to only build the differences since the last build.
2024-04-08 08:13:07 -07:00
Rose Thompson
b4b0cb81b9
Merge pull request #716 from davidharrishmc/dev
...
Fixed coremark to use wsim, more testfloat regression tests
2024-04-08 09:10:25 -05:00
David Harris
f5602d8b55
Ignore coremark_results
2024-04-08 05:57:50 -07:00
David Harris
60e70c1986
Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments.
2024-04-08 05:57:18 -07:00
David Harris
d182a2925e
Fixed bug in testbench_fp for XLEN > FLEN
2024-04-07 05:40:18 -07:00
David Harris
0b3bb72280
Added missing fdh_ieee_rv64gc derived config
2024-04-06 21:48:06 -07:00
David Harris
fec160d6f9
Updated coremark to use wsim
2024-04-06 21:38:44 -07:00
David Harris
76570ed2c2
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-06 20:51:46 -07:00
David Harris
dc6dc93b22
Merge pull request #712 from ross144/main
...
Fixed the buildroot vs +acc flag issue
2024-04-06 20:08:25 -07:00
David Harris
5092743365
Merge pull request #714 from jordancarlin/main
...
Update RISCOF ISA config MISA values to be consistent
2024-04-06 20:07:39 -07:00
Rose Thompson
7ec6c7ee51
Merge pull request #713 from Karl-Han/site_setup_fallback
...
Add fallback on site-setup.sh if no RISCV/site-setup.sh exists.
2024-04-06 20:24:39 -05:00
Jordan Carlin
6ef6bc042d
Update RISCOF ISA config MISA values to be consistent
2024-04-06 18:18:50 -07:00
Kunlin Han
fd2f88ef33
Add fallback on site-setup.sh if no RISCV/site-setup.sh exists.
2024-04-06 17:06:06 -07:00
Rose Thompson
bb072fba84
Fixed the buildroot issue.
2024-04-06 18:25:53 -05:00
David Harris
fb130edbf1
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-06 16:17:47 -07:00
David Harris
fe9b6129b8
Starting to add more testfloat
2024-04-06 16:17:42 -07:00
David Harris
b7b835f4eb
Merge pull request #711 from ross144/main
...
Got questa running with the wavefiles with unified do for testbench and testbench-fp
2024-04-06 16:16:29 -07:00
Rose Thompson
d0d1166e3f
Got the separation of the -G and +variable arguments in the questa do file.
...
regression still runs.
2024-04-06 18:04:48 -05:00
Rose Thompson
cdcff9d368
Updated sim-wally to work with new run scripts.
2024-04-06 16:32:07 -05:00
Rose Thompson
41845ec17e
Fixed issues around missing directories.
2024-04-06 16:29:58 -05:00
Rose Thompson
46fdfde7ec
Removed unnecessary display from testbench.
2024-04-06 16:10:18 -05:00
Rose Thompson
8885c32f7c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-04-06 15:55:00 -05:00
Rose Thompson
0a13cdf1d1
Merge pull request #710 from davidharrishmc/dev
...
Reorganized regression to support multiple simulations
2024-04-06 15:54:12 -05:00
David Harris
c73a48cf22
Removed unused wave-dos
2024-04-06 13:52:13 -07:00
David Harris
e8111da88a
Removed unused old regression-wally
2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e
Added GUI support and removed unused wave files
2024-04-06 13:43:06 -07:00
David Harris
d3d39d39d0
Buildroot regression passing
2024-04-06 11:50:25 -07:00
David Harris
3c855e3e90
Passing arguments to buildroot, not yet checking result correctly
2024-04-06 11:42:41 -07:00
David Harris
b3f007ec7f
Working on buildroot in regression
2024-04-06 11:11:22 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
David Harris
347df26713
Fixed regression running; buildroot pending
2024-04-06 09:46:56 -07:00
David Harris
9ee7544d3c
TestFloat running; normal testbench broken
2024-04-06 09:28:07 -07:00
David Harris
4b19f6d542
testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./
2024-04-06 08:22:39 -07:00
David Harris
4cc9dd7583
regression-wally refactoring to support mulitple simulators
2024-04-05 21:45:56 -07:00
David Harris
65fc8f6d51
Merge pull request #709 from slmnemo/main
...
Added ability to build linux testvectors directly using the makefile in the linux directory; UART outfile when performing a Linux boot test on the testbench
2024-04-05 21:42:57 -07:00
slmnemo
d107a42e8c
Replaced rewrite command with system rm command for uart file. Fixed comment on line 573
2024-04-05 21:39:41 -07:00
slmnemo
e631ae8c2d
Fixed sudo permissions in Linux Makefile, added nosudo versions of sudo commands
2024-04-05 21:38:30 -07:00
slmnemo
45cf997154
Removed extraneous whitespace
2024-04-05 21:05:10 -07:00
slmnemo
2fcae601a9
Replaced funky rewrite call with file removal
2024-04-05 20:59:08 -07:00
slmnemo
37716f1b56
Removed redundant lines from linux Makefile; gitignore
2024-04-05 20:53:52 -07:00
slmnemo
d89a187ce8
Fixed commit where Linux Makefile always built Linux into repo instead of into shared directory.
2024-04-05 20:44:11 -07:00
David Harris
7b56809323
wsim runs a Questa sim
2024-04-05 19:08:14 -07:00
David Harris
a1d3e5b15e
Moved do files into questa
2024-04-05 18:42:48 -07:00
David Harris
a8a03d6011
Reorganizing sim directory for multiple simulators
2024-04-05 18:19:46 -07:00
slmnemo
3ee25c8936
Merged testbench changes
2024-04-05 17:20:03 -07:00
