73 Commits

Author	SHA1	Message	Date
David Harris	74979cdc82	FDIV merge	2022-12-22 23:03:03 -08:00
David Harris	51b92285d3	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
cturek	04bc787647	Added negative-result int diviison support in U and UM registers. 13 tests pass!	2022-12-22 16:25:37 +00:00
cturek	1712e69c73	Moved swap from qslc to otfc	2022-12-22 15:44:50 +00:00
cturek	c7d0c8823f	Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.	2022-12-22 05:44:55 +00:00
cturek	c405dcf0cb	worked out some bugs with int div cycles	2022-12-22 02:22:01 +00:00
cturek	e441f90b32	Renamed signals to E and M stages, forwarded preprocessed n to fsm	2022-12-22 00:43:27 +00:00
cturek	14d9118802	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-21 19:35:57 +00:00
cturek	6761101645	fixed normshift calculations	2022-12-21 19:35:47 +00:00
David Harris	9133b3a7a4	FPU remove unused signals	2022-12-20 14:43:30 -08:00
Alessandro Maiuolo	13c9f2e4a5	Added NumZeroE, AZeroM, and BZeroM	2022-12-18 20:02:40 -08:00
Alessandro Maiuolo	3bcb42adb6	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
cturek	0ceecd9961	Added integer support for initC	2022-12-16 19:02:11 +00:00
cturek	9340a5eb49	Added mux for integer special case, renamed signals to match pipelined stage	2022-12-16 18:43:49 +00:00
David Harris	a285f289a6	Disabled starting FPU divider when IDIV_ON_FPU = 0	2022-12-16 06:35:29 -08:00
cturek	9f1aa7ad19	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-16 03:41:39 +00:00
David Harris	a8126458f6	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
David Harris	643a2e7cf9	Use FPU divider for integer division when F is supported	2022-12-14 17:03:13 -08:00
cturek	482caec42d	Fixed BZero and initU/initUM muxes	2022-12-14 16:44:46 +00:00
cturek	930fcbe956	Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs	2022-12-10 21:56:35 +00:00
Ross Thompson	350fdd944d	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." ... This reverts commit fb221d7b64.	2022-12-04 00:01:58 +00:00
cturek	fb221d7b64	Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.	2022-12-02 21:44:29 +00:00
cturek	04ac350a29	Added flops to preproc	2022-12-02 20:31:08 +00:00
David Harris	3a07d56d33	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
David Harris	1b0f878c16	Renamed DivStartE to IFDivStartE	2022-12-02 11:30:49 -08:00
David Harris	db5f3c15a4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
cturek	bdb9e24a66	Almost done with Int division	2022-11-22 22:22:59 +00:00
David Harris	59335ac70f	comment cleanup	2022-11-16 10:23:20 -08:00
David Harris	be9c618c94	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
David Harris	128cc86254	Moved DivStartE to fdivsqrtfsm	2022-11-16 10:00:07 -08:00
cturek	ffd03e9548	Attempt to fix FPGA synth errors	2022-11-15 20:34:28 +00:00
cturek	98b66aab9f	Fixed lint errors in postprocessing	2022-11-15 20:31:23 +00:00
cturek	abaa33b92a	Added majority of combinational logic	2022-11-14 00:06:38 +00:00
cturek	6740d77b63	Added Quotient/Remainder calcs to normal termination	2022-11-13 23:44:34 +00:00
cturek	12e3646153	Added flops for n and m, added B=0 signal	2022-11-13 23:02:43 +00:00
cturek	f10700e666	Added A<B signal to fdivsqrt, started postprocessing merge	2022-11-13 22:40:26 +00:00
David Harris	84c4558641	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-13 04:23:26 -08:00
David Harris	2ebdfa3f68	Comments about division hazards	2022-11-13 04:17:37 -08:00
cturek	4a8661649c	Added integer step counter to fsm	2022-11-11 00:23:25 +00:00
cturek	b723e16893	Fixed asign and bsign	2022-11-09 18:41:26 +00:00
cturek	d571b5f9a5	propagated otfc swap to Rad2 and 4 qslc	2022-11-06 23:32:38 +00:00
cturek	54f09f3616	Added conditional OTFC swap for simplified int postprocessing	2022-11-06 23:09:09 +00:00
cturek	c3e635c788	Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv	2022-11-06 22:40:21 +00:00
cturek	a49ea2a16d	Added n and rightshiftx	2022-11-06 22:31:48 +00:00
cturek	350d4d254f	p calculation	2022-11-06 22:24:21 +00:00
cturek	83051a5351	Changed lzc names, started int/fp size merge in preproc	2022-11-06 22:21:35 +00:00
cturek	2cbe2fd70b	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00
cturek	6bc4c1318e	Added new macros for int div preprocessing, added p, n, and rightshiftx logic	2022-11-06 21:53:48 +00:00
cturek	06a9305766	renamed remOp to RemOp	2022-11-03 22:37:25 +00:00
cturek	e37f564e84	Added rem/div operation to postprocessor	2022-11-02 17:49:40 +00:00