David Harris
735132191c
Moved muldiv result selection to M stage for performance
2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
a8573a27d4
Integer Divide/Rem passing all regression.
2021-09-30 20:07:22 -04:00
David Harris
953c8931ed
RV32 div/rem working signed and unsigned
2021-09-30 15:24:43 -04:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
David Harris
b2fe8eddc0
Restored old integer divider
2021-09-12 22:07:52 -04:00
David Harris
1f6e4c71fc
Modified rxfull determination in UART, started division
2021-09-12 20:00:24 -04:00
Ross Thompson
4c8ea89f15
Fixed syntax errors in some floating point modules. This came up in
...
Xilinx synthesis.
2021-08-15 16:48:49 -05:00
David Harris
b8b7fab02b
Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported
2021-07-04 19:33:46 -04:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
c016ab8e58
Commented out some unused modules
2021-07-04 01:40:27 -04:00
David Harris
9dd3857c26
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
Katherine Parry
b55798f09b
lint is clean
2021-06-07 14:22:54 -04:00
James E. Stine
7f5e5287b0
delete div.bak
2021-06-01 17:39:54 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
James E. Stine
927aec34a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
James E. Stine
a71b97e878
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
889b935630
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
James E. Stine
bbc1dfb309
Minor cosmetic elements on div.sv
2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877
Mod for DIV/REM instruction and update to div.sv unit
2021-05-24 19:29:13 -05:00
James E. Stine
49cc330bd9
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
James E. Stine
96eca3287f
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
David Harris
c9806fb472
Fixed lint error in div
2021-05-03 09:26:12 -04:00
Thomas Fleming
c055ab272d
Clean up lint errors in fpu and muldiv
...
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
Teo Ene
008b308b79
Fixed most relevant remaining synthesis compilation warnings with Ben
2021-04-21 16:06:27 -05:00
Teo Ene
0bffac2c74
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Ross Thompson
cb52820249
Fixed minor bug in muldiv which corrects the lint error.
2021-04-09 10:56:31 -05:00
Ross Thompson
a743acd1fd
Partial fix to the integer divide stall issue.
2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e
Minor cleanup
2021-04-02 08:20:44 -05:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
James E. Stine
59dee5580c
Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
2021-04-01 12:30:37 -05:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
f57096a5d2
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
David Harris
87ad559a90
Updated creation date of mul
2021-02-18 08:13:08 -05:00
David Harris
fe7299c155
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
e8d3c7d9e7
Multiplier tweaks
2021-02-17 16:00:27 -05:00
David Harris
e64e8afb7f
Started to integrate OSU divider
2021-02-17 15:38:44 -05:00
David Harris
a7dd20b388
Multiply instructions working
2021-02-17 15:29:20 -05:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
