Commit Graph

108 Commits

Author SHA1 Message Date
Ross Thompson
71f267a17a Added InstrUpdateDAF to the HPTW. 2024-06-19 11:09:49 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
David Harris
c1fd7a9589 Removed unused signals 2024-06-18 07:28:52 -07:00
David Harris
8bae52b09d Lint cleanup of unused signals 2024-06-18 06:49:17 -07:00
David Harris
3fa37b0233 Lint cleanup 2024-06-18 06:15:17 -07:00
David Harris
4a4bbdfc43 More code cleanup 2024-06-14 09:50:07 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
David Harris
86956026dc Further simplified subwordread muxing 2024-03-06 04:24:31 -08:00
David Harris
90e89ced1d Fixes for synthesis. HPTW change will break x detection 2024-02-26 04:20:08 -08:00
harshinisrinath
c7b647bde7 Wrote exclusions for ifu and lsu peripherals which were always supported 2024-02-01 17:12:33 -08:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
David Harris
1c1d3eb956 HPTW coverage improvements 2024-01-26 10:46:38 -08:00
David Harris
2449e06e55 Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported 2024-01-25 21:03:41 -08:00
David Harris
171430a695 FPU and PMP tests 2024-01-21 14:41:22 -08:00
David Harris
911b400af2 Fault on misaligned AMO 2024-01-18 13:13:56 -08:00
Rose Thompson
e8474373e4 Fixed it so Virtual Memory work without a D$. 2024-01-18 09:18:17 -06:00
David Harris
67124b0c7f Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough 2024-01-06 07:11:25 -08:00
David Harris
0781cd4a44 Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate 2024-01-05 22:45:15 -08:00
Rose Thompson
1f3792c823 Fixed bug # 547, but there are other bugs which follow. 2024-01-05 23:32:10 -06:00
Rose Thompson
edc56c669e Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
David Harris
680a014876 Finished LSU tlbcontrol coverage tests 2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE 2024-01-02 00:35:17 -08:00
David Harris
c52aef86a6 Fixed coverage exclusions that no longer reference code properly 2023-12-31 20:35:08 -08:00
David Harris
536539237c Fixed exclusion tags in pmachecker 2023-12-31 20:20:31 -08:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
David Harris
6395cd0284 Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match 2023-12-21 12:29:37 -08:00
Rose Thompson
b68dd74f89 Reverted logic to bit change. 2023-12-20 13:16:32 -06:00
Rose Thompson
18a96740d5 Revert RAM logic to bit change.
Added logic to hptw to prevent x propagation.
2023-12-20 13:10:20 -06:00
David Harris
166c98b6f6 Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn 2023-12-13 19:43:17 -08:00
David Harris
333e390f8d Test commit from dev 2023-12-13 11:52:21 -08:00
David Harris
6c017141c5 Renamed HADE to ADUE for Svadu 2023-12-13 11:49:04 -08:00
Rose Thompson
f11f88ac2b Updates to tlb to check access permissions for cbo* 2023-11-29 16:20:43 -06:00
Rose Thompson
f4e4aac8b5 Added CMOp to pmp checker 2023-11-29 16:09:31 -06:00
Rose Thompson
fc04b6f7d8 Removed redundant ZICBOM/Z_SUPPORTED from pmachecker. 2023-11-29 15:39:39 -06:00
Rose Thompson
053b094620 Simpilified pmachecker for cmo. 2023-11-29 12:26:18 -06:00
Rose Thompson
9a24a5d957 Renamed signal in pmachecker. 2023-11-28 00:05:12 -06:00
Rose Thompson
9290c3f957 Added correct cbo fault behavior. 2023-11-27 20:57:33 -06:00
Rose Thompson
beb95dd592 Modified the pmachecker to correctly check the permissions for cmo instructions.
However this isn't fully tested.
2023-11-27 17:44:11 -06:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
naichewa
a08356fdaa correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
Rose Thompson
2241976d29 Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
2023-10-30 18:26:11 -05:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
David Harris
19a6bbb01b UpdateDA cleanup: don't assert UpdateDA when there is no SVADU 2023-10-04 09:57:13 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
David Harris
9747d122d2 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
David Harris
8d3ff59673 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
David Harris
f7b50f4721 Preparing to merge with CBO* changes 2023-08-25 18:41:03 -07:00