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3,920 Commits 5 Branches 2 Tags 53 MiB
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117 Commits

Author SHA1 Message Date
Ross Thompson
05484c4c05 signal name cleanup. 2022-07-22 23:36:27 -05:00
Katherine Parry
12a54161c0 found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
62205ebb3b renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
David Harris
72e216d053 APB CLINT passing regression 2022-07-05 15:51:35 +00:00
Katherine Parry
8f98f3bfab added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
slmnemo
be658d3933 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
slmnemo
a5aa75e5de Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
slmnemo
90c5e5d319 Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
David Harris
129fab3794 Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
slmnemo
efce3e4953 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
slmnemo
80965f953c added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
David Harris
5acb526375 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
fb725a9e0a Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
8066ba45e8 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
Ross Thompson
ab9738d3be Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
7a824eaae1 Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
Ross Thompson
58668812c1 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Ross Thompson
c5be2cb1d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
cec7625d91 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Ross Thompson
d347de8c49 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445 Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
50789f9ddd Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
Ross Thompson
ed32801cc1 Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
acd60218b8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
60e6c1ffa7 Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
Ross Thompson
6a52f95cc8 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
56fc6d0d7c Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
Ross Thompson
f48b12b089 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
ae06785b9f Minor changes to LSU. 2022-02-19 14:38:17 -06:00
Ross Thompson
0eec096474 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00