Katherine Parry
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701ea38964
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Katherine Parry
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f8b76082e4
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fpu unpacking unit created
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2021-07-14 17:56:49 -04:00 |
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bbracker
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04ce2f7256
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testvector unlinker for dev purposes
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2021-07-14 11:05:34 -04:00 |
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James Stine
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a2c0753edb
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put back for now to test fdiv
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2021-07-14 06:48:29 -05:00 |
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Abe
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853e1167a2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 04:47:31 -04:00 |
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Abe
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a823190ce4
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Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use
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2021-07-14 04:46:11 -04:00 |
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bbracker
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9b6d45ead9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 00:21:39 -04:00 |
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bbracker
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61e6ebd4d3
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make testvector scripts agree with new file structure; use symbols to determine end of linux boot
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2021-07-14 00:21:29 -04:00 |
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bbracker
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eb8c1bf5e7
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needed to create a directory for gdb script
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2021-07-13 19:39:57 -04:00 |
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Abe
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8d445ef508
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 18:22:36 -04:00 |
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James E. Stine
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45a6e96673
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mod 2 of fpdivsqrt update
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2021-07-13 16:59:17 -04:00 |
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James E. Stine
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d695be3ad0
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Update fpdivsqrt item until move into uarch
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2021-07-13 16:53:20 -04:00 |
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bbracker
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2036be2ea4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 16:16:04 -04:00 |
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bbracker
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dff3970d1c
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changed QEMU to use different ports
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2021-07-13 16:15:51 -04:00 |
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David Harris
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516b710db6
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Fixed busybear by restoring InstrValidW needed by testbench
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2021-07-13 14:17:36 -04:00 |
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Abe
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d71b99383f
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Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally
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2021-07-13 13:37:40 -04:00 |
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David Harris
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9af5cef65a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 13:26:51 -04:00 |
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David Harris
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283c2cda0e
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added or.sv
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2021-07-13 13:26:40 -04:00 |
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Katherine Parry
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b9edbb15eb
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Fixed writting MStatus FS bits
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2021-07-13 13:22:04 -04:00 |
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Katherine Parry
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acdd2e4504
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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David Harris
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3427d2b7d6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 13:19:24 -04:00 |
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David Harris
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68d1f87101
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Fixed InstrValid from W to M stage for CSR performance counters
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2021-07-13 13:19:13 -04:00 |
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bbracker
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90eb84cc61
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updated buildroot make procedure to incorporate configs more robustly
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2021-07-13 12:40:14 -04:00 |
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bbracker
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471fe8ab31
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whoops I accidentally made main.config into a symbolic link; now it is a source file
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2021-07-13 11:00:01 -04:00 |
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bbracker
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be81912c52
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 10:04:13 -04:00 |
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bbracker
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497d8e3f16
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working config for a buildroot that boots
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2021-07-13 10:04:09 -04:00 |
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David Harris
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4be1e8617f
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Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
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2021-07-13 09:32:02 -04:00 |
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Katherine Parry
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a4bd128978
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fcvt.sv cleanup
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2021-07-11 21:30:01 -04:00 |
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Katherine Parry
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0cc07fda1b
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
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bbracker
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05f9fa65bf
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rootfs.cpio no longer overlaps
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2021-07-11 05:11:12 -04:00 |
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bbracker
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e77a9169b6
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greatly stripped down unused stuff in linux config
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2021-07-10 11:53:35 -04:00 |
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David Harris
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488cfa16ff
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-09 19:18:35 -04:00 |
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David Harris
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e6fb590187
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added missing tlbmixer.sv
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2021-07-09 19:18:23 -04:00 |
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bbracker
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4556098f0a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-09 18:56:28 -04:00 |
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bbracker
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e4f62e32ba
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fix_mem.py bugfix
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2021-07-09 18:56:17 -04:00 |
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bbracker
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b2cb86d55c
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organize/update buildroot scripts for new image
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2021-07-09 17:03:47 -04:00 |
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David Harris
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ef2bcf6ea7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-09 07:53:30 -04:00 |
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David Harris
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b09fd0d0a8
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Simplified tlbmixer mux to and-or
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2021-07-08 23:34:24 -04:00 |
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David Harris
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4d53a935b3
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Fixed missing stall in InstrRet counter
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2021-07-08 20:08:04 -04:00 |
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bbracker
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5736fdecbb
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organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
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2021-07-08 19:18:11 -04:00 |
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David Harris
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230654ea76
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Eliminate reserved bits from TLB RAM
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2021-07-08 17:35:00 -04:00 |
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David Harris
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f806707cb0
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Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
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2021-07-08 16:58:11 -04:00 |
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David Harris
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b1592a0542
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TLB cleanup to match diagrams
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2021-07-08 16:52:06 -04:00 |
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David Harris
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dc44ca4b0b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-07 06:32:29 -04:00 |
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David Harris
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6dc49dd073
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Renamed tlb ReadLines to Matches
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2021-07-07 06:32:26 -04:00 |
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Abe
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09a092abd5
|
Updated MISA defining as well as porting sizes for peripherals (34 to 56)
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2021-07-07 02:37:09 -04:00 |
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Abe
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ed3c06b851
|
Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time.
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2021-07-07 02:28:11 -04:00 |
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Abe
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ab61590f77
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Removed debugging loop to test timers for clarity
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2021-07-06 23:37:43 -04:00 |
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Abe
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63e4db1158
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Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120
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2021-07-06 23:35:47 -04:00 |
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Abe
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244e197348
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Changed SvMode to SVMode on line 76
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2021-07-06 23:28:58 -04:00 |
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