Ross Thompson
6f3b8680d5
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 09:41:18 -06:00
Ross Thompson
87c1f285c1
Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas
2023-01-20 08:38:08 -06:00
Lee Moore
e1e693a1d2
Merge pull request #13 from eroom1966/imperas
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Merge pull request #5 from davidharrishmc/imperas
2023-01-20 14:34:38 +00:00
Lee Moore
cddc111cd6
Merge pull request #5 from davidharrishmc/imperas
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Merge pull request #12 from eroom1966/imperas
2023-01-20 14:33:21 +00:00
Lee Moore
56eeb7cf9b
Merge pull request #12 from eroom1966/imperas
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Imperas
2023-01-20 14:32:57 +00:00
Lee Moore
3427f7de20
Merge pull request #4 from davidharrishmc/imperas
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Merge pull request #11 from eroom1966/imperas
2023-01-20 14:32:21 +00:00
eroom1966
70f8c7a14e
Merge branch 'imperas' of https://github.com/eroom1966/riscv-wally into imperas
2023-01-20 14:31:17 +00:00
Lee Moore
fe4f8428ca
Merge pull request #11 from eroom1966/imperas
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Imperas
2023-01-19 14:56:44 +00:00
Lee Moore
35a6e407b6
Merge branch 'davidharrishmc:imperas' into imperas
2023-01-19 14:56:18 +00:00
eroom1966
43d5769bd9
update
2023-01-19 13:29:46 +00:00
eroom1966
5212499513
correct the HASH
2023-01-19 10:41:11 +00:00
Lee Moore
e12867af8e
Merge pull request #10 from eroom1966/imperas
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Imperas
2023-01-19 10:28:27 +00:00
Lee Moore
d12758675c
Merge pull request #3 from davidharrishmc/imperas
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Imperas
2023-01-19 10:27:52 +00:00
eroom1966
f9b14ccdc5
customer commands
2023-01-19 10:20:55 +00:00
Ross Thompson
c2fe8c3f27
Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas
2023-01-18 16:04:02 -06:00
Ross Thompson
474f934fd1
Modified to clone imperas via git rather than https.
2023-01-18 15:49:42 -06:00
Lee Moore
2b07812051
Merge pull request #9 from eroom1966/imperas
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Partial fix for misaligned LD/ST
2023-01-18 17:12:19 +00:00
eroom1966
8dea3491a3
Partial fix for misaligned LD/ST
2023-01-18 17:11:39 +00:00
Lee Moore
a032a9a174
Merge pull request #8 from eroom1966/imperas
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changes made with Ross
2023-01-18 16:48:22 +00:00
eroom1966
0ccab9accc
changes made with Ross
2023-01-18 16:46:48 +00:00
ross144
786d7839ff
Merge pull request #7 from eroom1966/imperas
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Imperas
2023-01-18 09:27:39 -06:00
eroom1966
247879e7c7
add im flags for compressed disass
2023-01-18 13:37:28 +00:00
eroom1966
52ebac59b8
remove volatile for FFLAGS and FCSR
2023-01-18 13:33:57 +00:00
eroom1966
68af12ece1
refer to correct path
2023-01-18 13:26:07 +00:00
eroom1966
7a4472f94e
ignore external
2023-01-18 13:22:32 +00:00
eroom1966
c120717027
update for private copy of Imperas
2023-01-18 13:19:14 +00:00
Lee Moore
2b43afba01
Merge pull request #2 from davidharrishmc/imperas
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Imperas
2023-01-18 09:14:07 +00:00
Ross Thompson
374f95ebf3
Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage.
2023-01-17 18:24:46 -06:00
ross144
19230426d4
Merge pull request #2 from eroom1966/imperas
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Imperas
2023-01-17 14:50:05 -06:00
eroom1966
cf3223df22
refactor all rvvi into single initial block
2023-01-17 13:01:01 +00:00
eroom1966
2ead2cdaf4
Code refactor and addition of rvvi interface
2023-01-17 12:47:38 +00:00
Lee Moore
485b041f02
Merge pull request #1 from davidharrishmc/imperas
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Imperas
2023-01-17 09:23:41 +00:00
Ross Thompson
1680f89ef3
Found a potential issue with mstatush when XLEN = 64.
2023-01-16 13:57:28 -06:00
Ross Thompson
7984194c2a
Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs.
2023-01-16 13:35:06 -06:00
Ross Thompson
53c8042276
Signal renames for ras.
2023-01-13 15:56:10 -06:00
Ross Thompson
8e3e8591a6
Removed 1 bit from instruction classification.
2023-01-13 15:19:53 -06:00
Ross Thompson
37481fce77
More branch predictor cleanup.
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Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
2023-01-13 12:57:18 -06:00
Ross Thompson
b26cec1ef4
Possible optimization of gshare.
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I don't believe the Writeback stage ghr is needed.
2023-01-13 12:39:29 -06:00
Ross Thompson
f7dacb59f9
Possible minor enhancement to gshare.
2023-01-13 12:32:39 -06:00
Ross Thompson
14ecaabbf6
Nearly complete RVVI tracer.
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Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
2023-01-12 18:43:39 -06:00
Ross Thompson
59b135d895
Added supervisor mode registers to tracer.
2023-01-12 17:04:41 -06:00
Ross Thompson
6500321aaf
Added M CSRs to the CSRArray.
2023-01-12 16:51:51 -06:00
Ross Thompson
8981739310
added machine csr to logger.
2023-01-12 16:35:19 -06:00
Ross Thompson
f3443e2eca
Added support to print the gprs.
2023-01-12 16:09:30 -06:00
Ross Thompson
0ea0e7a9e1
rvvi trace is coming alone nicely.
2023-01-12 14:46:31 -06:00
Ross Thompson
9a180f88f7
Completely stripped down imperas simulation.
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run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
2023-01-12 12:48:38 -06:00
Ross Thompson
5112ffcbc9
Stripped out all signature checking.
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Removed multiple tests loop.
Only runs 1 test now.
2023-01-12 12:45:44 -06:00
Ross Thompson
8ee80c5d54
Created separate imperas testbench.
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Resolved logger issue with the duplicated instructions after commit.
2023-01-12 12:07:07 -06:00
Ross Thompson
f59e1d03fc
Added instruction logger.
2023-01-12 10:09:34 -06:00
Ross Thompson
3a41854f2b
Completed review of LSU.
2023-01-11 19:06:03 -06:00
