Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
680a014876
Finished LSU tlbcontrol coverage tests
2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
18a96740d5
Revert RAM logic to bit change.
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Added logic to hptw to prevent x propagation.
2023-12-20 13:10:20 -06:00
David Harris
333e390f8d
Test commit from dev
2023-12-13 11:52:21 -08:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
Ross Thompson
c0966c32e5
Improved critical path.
2023-07-19 14:59:37 -05:00
Harshini Srinath
a57a619349
Update hptw.sv
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Program clean up
2023-06-12 18:31:38 -07:00
Ross Thompson
8e1476cb8c
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Ross Thompson
0020d94b39
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
David Harris
af7959a3e2
Commenting
2023-04-28 07:52:08 -07:00
Ross Thompson
e531b0103e
Fixed wally64/32priv test hangup.
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The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Ross Thompson
394f2d65f2
Progress on bug 203.
2023-04-05 13:20:04 -05:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
Ross Thompson
e448cd54ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-06 18:39:15 -06:00
Ross Thompson
31fcc0daf7
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
David Harris
23775c6d67
Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA
2023-03-01 11:18:00 -08:00
David Harris
f40352e82b
hptw typo fix
2023-02-26 19:38:34 -08:00
David Harris
e9ad6ae057
Simplified Access fault logic in HPTW
2023-02-26 18:50:37 -08:00
David Harris
21b28fd1bb
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
David Harris
4274071333
renamed UpperBitsUnequalPageFault to UpperBitsUnequal
2023-02-26 17:32:34 -08:00
David Harris
35653a18b7
Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
2023-02-26 09:38:32 -08:00
David Harris
f31764c3e1
Renamed DAPageFault to HPTWDAPageFault in hptw to avoid name conflict with DAPageFault from tlbcontrol
2023-02-26 07:12:43 -08:00
Ross Thompson
c33230d1c1
Fixed Bug 66.
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If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
2023-02-06 17:32:28 -06:00
Ross Thompson
4e8ef4a0ac
Removed unreachable if branch in hptw next state logic.
2023-02-06 16:42:07 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
