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303 lines
16 KiB
Systemverilog
303 lines
16 KiB
Systemverilog
///////////////////////////////////////////
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// hptw.sv
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//
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// Written: tfleming@hmc.edu 2 March 2021
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// Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification
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// kmacsaigoren@hmc.edu 1 June 2021
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// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
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// adding support for terapage encoding, and for setting the HPTWAdr using the new level,
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// adding the internal SvMode signal
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//
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// Purpose: Hardware Page Table Walker
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module hptw (
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input logic clk, reset,
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input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
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input logic [`XLEN-1:0] PCFSpill, // addresses to translate
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input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
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input logic [1:0] MemRWM, AtomicM,
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// system status
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] ReadDataM, // page table entry from LSU
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input logic [`XLEN-1:0] WriteDataM,
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input logic DCacheStallM, // stall from LSU
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic ITLBMissF,
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input logic DTLBMissM,
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input logic FlushW,
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input logic InstrDAPageFaultF,
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input logic DataDAPageFaultM,
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output logic [`XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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output logic [1:0] PreLSURWM,
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output logic [`XLEN+1:0] IHAdrM,
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output logic [`XLEN-1:0] IHWriteDataM,
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output logic [1:0] LSUAtomicM,
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output logic [2:0] LSUFunct3M,
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output logic [6:0] LSUFunct7M,
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output logic IgnoreRequestTLB,
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output logic SelHPTW,
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output logic HPTWStall,
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input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM,
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output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM
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);
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typedef enum logic [3:0] {L0_ADR, L0_RD,
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L1_ADR, L1_RD,
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L2_ADR, L2_RD,
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L3_ADR, L3_RD,
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LEAF, IDLE, UPDATE_PTE} statetype;
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logic DTLBWalk; // register TLBs translation miss requests
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic Executable, Writable, Readable, Valid, PTE_U;
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logic Misaligned, MegapageMisaligned;
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logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
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logic StartWalk;
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logic TLBMiss;
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logic PRegEn;
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logic [1:0] NextPageType;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`XLEN-1:0] NextPTE;
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logic UpdatePTE;
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logic HPTWDAPageFault;
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logic [`PA_BITS-1:0] HPTWReadAdr;
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logic SelHPTWAdr;
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logic [`XLEN+1:0] HPTWAdrExt;
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logic ITLBMissOrDAFaultF;
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logic DTLBMissOrDAFaultM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic [1:0] HPTWRW;
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logic [2:0] HPTWSize; // 32 or 64 bit access
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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// map hptw access faults onto either the original LSU load/store fault or instruction access fault
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assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0];
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assign StoreAmoAccessFaultM = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[0];
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assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: (LSUStoreAmoAccessFaultM | LSULoadAccessFaultM) & ~DTLBWalk;
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// Extract bits from CSRs and inputs
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF);
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// Determine which address to translate
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mux2 #(`XLEN) vadrmux(PCFSpill, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
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assign CurrentPPN = PTE[`PPN_BITS+9:10];
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// State flops
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flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
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assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE;
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flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
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// Assign PTE descriptors common across all XLEN values
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// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
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assign {PTE_U, Executable, Writable, Readable, Valid} = PTE[4:0];
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid & ~(Writable & ~Readable);
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assign ValidLeafPTE = ValidPTE & LeafPTE;
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assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
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if(`SVADU_SUPPORTED) begin : hptwwrites
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logic ReadAccess, WriteAccess;
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logic InvalidRead, InvalidWrite;
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logic UpperBitsUnequalPageFault;
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logic OtherPageFault;
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logic [1:0] EffectivePrivilegeMode;
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logic ImproperPrivilege;
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logic SaveHPTWAdr, SelHPTWWriteAdr;
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logic [`PA_BITS-1:0] HPTWWriteAdr;
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logic SetDirty;
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logic Dirty, Accessed;
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logic [`XLEN-1:0] AccessedPTE;
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assign AccessedPTE = {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
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mux2 #(`XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
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flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
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assign SaveHPTWAdr = WalkerState == L0_ADR;
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assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0];
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mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr);
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assign {Dirty, Accessed} = PTE[7:6];
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assign WriteAccess = MemRWM[0] | (|AtomicM);
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assign SetDirty = ~Dirty & DTLBWalk & WriteAccess;
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assign ReadAccess = MemRWM[1];
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assign EffectivePrivilegeMode = DTLBWalk ? (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW) : PrivilegeModeW; // DTLB uses MPP mode when MPRV is 1
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assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
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((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
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// Check for page faults
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vm64check vm64check(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), .VAdr(TranslationVAdr),
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.SV39Mode(), .UpperBitsUnequalPageFault);
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assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
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assign InvalidWrite = WriteAccess & ~Writable;
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assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
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ImproperPrivilege | ~Executable | UpperBitsUnequalPageFault | Misaligned | ~Valid;
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// hptw needs to know if there is a Dirty or Access fault occuring on this
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// memory access. If there is the PTE needs to be updated seting Access
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// and possibly also Dirty. Dirty is set if the operation is a store/amo.
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// However any other fault should not cause the update.
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assign HPTWDAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
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assign HPTWRW[0] = (WalkerState == UPDATE_PTE);
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assign UpdatePTE = (WalkerState == LEAF) & HPTWDAPageFault;
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end else begin // block: hptwwrites
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assign NextPTE = ReadDataM;
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assign HPTWAdr = HPTWReadAdr;
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assign HPTWDAPageFault = '0;
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assign UpdatePTE = '0;
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assign HPTWRW[0] = '0;
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end
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// Enable and select signals based on states
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assign StartWalk = (WalkerState == IDLE) & TLBMiss;
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assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
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assign DTLBWriteM = (WalkerState == LEAF & ~HPTWDAPageFault) & DTLBWalk;
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assign ITLBWriteF = (WalkerState == LEAF & ~HPTWDAPageFault) & ~DTLBWalk;
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// FSM to track PageType based on the levels of the page table traversed
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flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
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always_comb
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case (WalkerState)
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L3_RD: NextPageType = 2'b11; // terapage
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L2_RD: NextPageType = 2'b10; // gigapage
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L1_RD: NextPageType = 2'b01; // megapage
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L0_RD: NextPageType = 2'b00; // kilopage
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default: NextPageType = PageType;
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endcase
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// HPTWAdr muxing
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if (`XLEN==32) begin // RV32
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logic [9:0] VPN;
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logic [`PPN_BITS-1:0] PPN;
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assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
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assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
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assign HPTWReadAdr = {PPN, VPN, 2'b00};
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assign HPTWSize = 3'b010;
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end else begin // RV64
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logic [8:0] VPN;
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logic [`PPN_BITS-1:0] PPN;
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always_comb
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case (WalkerState) // select VPN field based on HPTW state
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L3_ADR, L3_RD: VPN = TranslationVAdr[47:39];
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L2_ADR, L2_RD: VPN = TranslationVAdr[38:30];
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L1_ADR, L1_RD: VPN = TranslationVAdr[29:21];
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default: VPN = TranslationVAdr[20:12];
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endcase
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assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
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(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
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assign HPTWReadAdr = {PPN, VPN, 3'b000};
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assign HPTWSize = 3'b011;
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end
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// Initial state and misalignment for RV32/64
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if (`XLEN == 32) begin
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assign InitialWalkerState = L1_ADR;
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assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
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assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
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end else begin
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logic GigapageMisaligned, TerapageMisaligned;
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assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
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assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
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assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
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assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
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assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
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end
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// Page Table Walker FSM
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// there is a bug here. Each memory access needs to be potentially flushed if the PMA/P checkers
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// generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation.
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// I think the solution is to do 1 of the following
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// 1. Allow the HPTW to generate exceptions and stop walking immediately.
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// 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back
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// to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but
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// rather than physical address of the translated instruction/data. So we must generate the exception.
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb
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case (WalkerState)
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IDLE: if (TLBMiss & ~DCacheStallM) NextWalkerState = InitialWalkerState;
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else NextWalkerState = IDLE;
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;
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else NextWalkerState = L2_ADR;
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L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
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else NextWalkerState = LEAF;
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L2_RD: if (DCacheStallM) NextWalkerState = L2_RD;
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else NextWalkerState = L1_ADR;
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L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
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else NextWalkerState = LEAF;
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L1_RD: if (DCacheStallM) NextWalkerState = L1_RD;
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else NextWalkerState = L0_ADR;
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L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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LEAF: if (`SVADU_SUPPORTED & HPTWDAPageFault) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = IDLE;
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UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = LEAF;
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default: NextWalkerState = IDLE; // should never be reached
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endcase // case (WalkerState)
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assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss;
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assign SelHPTW = WalkerState != IDLE;
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assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss);
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assign ITLBMissOrDAFaultF = ITLBMissF | (`SVADU_SUPPORTED & InstrDAPageFaultF);
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assign DTLBMissOrDAFaultM = DTLBMissM | (`SVADU_SUPPORTED & DataDAPageFaultM);
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// HTPW address/data/control muxing
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// Once the walk is done and it is time to update the TLB we need to switch back
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// to the orignal data virtual address.
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assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
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// always block interrupts when using the hardware page table walker.
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// multiplex the outputs to LSU
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if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
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else assign HPTWAdrExt = HPTWAdr;
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mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
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if(`SVADU_SUPPORTED)
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mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
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else assign IHWriteDataM = WriteDataM;
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endmodule
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// another idea. We keep gating the control by ~FlushW, but this adds considerable length to the critical path.
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// should we do this differently? For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives
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// the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit.
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