Ross Thompson
8fa287a449
The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
2021-09-17 10:33:57 -05:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
bb3e94d68a
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
c954fb510b
Renamed DCacheStall to LSUStall in hart and hazard.
...
Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Ross Thompson
ee09fa5f58
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
Ross Thompson
549b7b2a62
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
Katherine Parry
bc8d660bc5
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
Katherine Parry
b55798f09b
lint is clean
2021-06-07 14:22:54 -04:00
Katherine Parry
e4db6ea6f5
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Katherine Parry
65eca433b6
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
55f22979ca
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
Jarred Allen
6ce4d44ae1
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Ross Thompson
a743acd1fd
Partial fix to the integer divide stall issue.
2021-04-02 15:32:15 -05:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Jarred Allen
fdecd6c56c
Clean up some stuff
2021-03-25 13:04:54 -04:00
Jarred Allen
15e786da0b
Working for all of rv64i now, but not compressed instructions
2021-03-25 13:02:26 -04:00
Jarred Allen
e8e4e1bee2
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
Jarred Allen
c0ee17b6ac
Merge upstream changes
2021-03-09 21:20:34 -05:00
Jarred Allen
5da98b5381
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
225102047a
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
adc5d5bc1a
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
b121b90b28
Debugging bus interface.
2021-02-10 01:43:54 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
616830a3f0
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
229bde5953
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
