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574 Commits 5 Branches 2 Tags 53 MiB
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267 Commits

Author SHA1 Message Date
bbracker
d52c71086a added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
ca392225df added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
6edb055f26 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
5327dcfcc8 instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
a8b7d7a248 upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
3e656fc035 future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
f2604797fb Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Katherine Parry
123e63b440 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Jarred Allen
0776127c75 Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
abf9f3b3cb Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Jarred Allen
1f01a12be9 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Katherine Parry
fb78dedae2 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Jarred Allen
ebd2c60b74 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
8556c07261 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Shreya Sanghai
09b90557f7 PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
34cc9b4aeb Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
e4ebb4e31e Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
c47a80213e Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
bbracker
c3a6d6bf42 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
307e33bc7e Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Jarred Allen
2269879459 Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
9af0ad815c fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Jarred Allen
066dc2caac Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
e531a1b5ee Merge branch 'main' into cache 2021-03-20 17:56:25 -04:00
Jarred Allen
665c244ba1 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354 Revert "Change flop to listen to StallF" 
This reverts commit f069b759be.
 2021-03-20 17:34:19 -04:00
Jarred Allen
f069b759be Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Katherine Parry
fd381e60d7 messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
bbracker
df51d9908d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
11ba96f2e3 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
181a28e875 Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
f35d3b39c8 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
859d242d81 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Noah Boorstin
847bf0b9a6 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3 everyone gets a bootram 2021-03-18 12:35:37 -04:00
Shreya Sanghai
d9b1e7d67f added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Jarred Allen
3fc36b978d Fix icache for jumping into misaligned instructions 2021-03-16 16:57:51 -04:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
98db312574 Merge remote-tracking branch 'origin/main' into cache 2021-03-16 14:17:39 -04:00
Shreya Sanghai
23a7c8cd92 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
518618ad38 Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Jarred Allen
5b174adc2a Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
c2f2caa3f6 Get non-jump case working 2021-03-14 14:46:21 -04:00
bbracker
b30ea396b8 slightly smarter dtim HREADY 2021-03-13 07:03:33 -05:00
bbracker
63bfd79009 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
12721837f0 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
bbracker
0f49108ee6 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
fe4d288589 Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Noah Boorstin
2d1f63b590 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891 More progress 2021-03-09 21:16:07 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
David Harris
52d4a04eb0 Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
ca2a65770c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
bbracker
612f7a9ee4 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
a1223ee13b more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
2cd0f19129 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
62dd9e3075 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Thomas Fleming
97e9baa316 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
0af002eb2f busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Ross Thompson
a982ad7a9a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
5374dca1b9 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a fixed various bugs 2021-03-04 22:18:19 +00:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Thomas Fleming
38bd683f2d Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
5c456e2d7f busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Shreya Sanghai
f95a1eadd9 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
7cd8f1a592 added performance counters 2021-03-04 11:42:52 -05:00
Ross Thompson
d0223da2f7 Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00