Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Jacob Pease
2839f4f41a
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Jacob Pease
b796b1b492
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Jacob Pease
2d0199a354
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Jacob Pease
449b835fcd
Disabled old SD card and attached IOBUF's to new SD peripheral.
2023-02-28 12:20:46 -06:00
Jacob Pease
85d789a7e0
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
45b264fa59
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
Jacob Pease
f2e4274c9c
Fixed debug signal names. Builds on the fpga. Bug in the crossbar.
2023-02-16 17:33:21 -06:00
Ross Thompson
ff7dc4f34a
fpga constraints updates
2023-02-07 15:22:14 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Jacob Pease
c36d32f850
Flipped crossbar inputs and outputs to correctly place masters.
2023-01-27 14:57:36 -06:00
Jacob Pease
264f0ba0da
Removed IOBUF's from sdc_controller.
2023-01-27 14:35:34 -06:00
Jacob Pease
07e279b5b5
Modified makefile. Added axi protocol converter IP.
2023-01-23 19:30:29 -06:00
Jacob Pease
c8d487b9e6
Created missing wires for axi interfaces in fpgaTop.v.
2023-01-23 19:02:01 -06:00
Jacob Pease
293cc88bd9
Added extra core signal to mark_debug.txt. Modified wally.tcl
2023-01-23 17:00:24 -06:00
Jacob Pease
9b612fbf6c
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-01-23 12:41:02 -06:00
Ross Thompson
2fc47bab9c
More fixes for the debug2.xdc constraints.
2023-01-20 20:48:19 -06:00
Ross Thompson
61efb22db1
More fixes to fpga ila debugger.
2023-01-20 20:28:21 -06:00
Ross Thompson
e28ea2d630
Fixed fpga constraints.
2023-01-20 20:18:04 -06:00
Ross Thompson
0ed9811e31
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
4ccea17648
Added license and comments to new script.
2023-01-20 19:50:33 -06:00
Ross Thompson
9c83b2dff5
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
25bd2e4670
Removed mark_debug vivado directive from source code.
...
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
6ccb3a0147
Test commit.
2023-01-20 17:27:09 -06:00
Ross Thompson
11c6106022
Repaired fpga debugger.
2023-01-20 15:26:52 -06:00
Ross Thompson
5b740fbf60
Removed SDC from repo due to copy right issue.
...
Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Jacob Pease
12b379ebd8
Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error.
2023-01-19 16:57:43 -06:00
Jacob Pease
ee3a9537a8
Fixed errors in uncore and included newsdc stuff in wally.tcl
2023-01-17 16:46:00 -06:00
Jacob Pease
b618518907
Fixed typos. Apparently `defube causes a weird vivado error.
2023-01-13 16:59:18 -06:00
Jacob Pease
dcfb68daee
Added IPs to wally.tcl.
2023-01-13 14:36:23 -06:00
Jacob Pease
e5d4277406
Connected the axi_sdc_controller with an axi crossbar.
...
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
2023-01-13 13:56:01 -06:00
Ross Thompson
e0ec45489a
Updated constraints to remove DivBusyE.
2022-12-30 10:51:35 -06:00
Ross Thompson
138c3542db
Updated fpga constraints.
2022-12-24 10:21:16 -06:00
Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
15042fc856
Updated fpga constraints.
2022-12-21 14:50:01 -06:00
Ross Thompson
13beda7d0c
Updated vcu118 piniout.
2022-12-18 14:00:10 -06:00
Ross Thompson
3ee6ed8542
Updated fpga constraints
2022-12-15 16:45:55 -06:00
rachanaerra
10ff69efc1
updated constraints file
2022-12-05 15:05:21 -06:00
Ross Thompson
e99a424ddc
Updated top level fpga file.
2022-11-18 11:10:45 -06:00
Ross Thompson
70d7fca750
Updated fpga wave configuration.
2022-11-16 15:57:19 -06:00
Ross Thompson
cf00f85456
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
cc80f1f7b2
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
30b2bd263c
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
Ross Thompson
5c49cc4dd0
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Jacob Pease
160ca366c8
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
Ross Thompson
9ba487c323
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
92ace4d8f7
Forget to include updated xdc file.
2022-10-24 13:51:21 -05:00
