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818 Commits

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Author SHA1 Message Date
ushakya22
6a71aafadc Updated CSR tests 2021-05-04 13:48:47 -04:00
Ross Thompson
87d3869a6e Fixed icache pcmux control for handling miss spill miss. 2021-05-04 11:05:01 -05:00
Thomas Fleming
192878b124 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 03:14:38 -04:00
Thomas Fleming
dac07e34cf Fix bug in PMP checker 
Now we only enforce PMP regions if at least one is non-null
 2021-05-04 03:14:07 -04:00
ushakya22
da352c81e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
66344f0604 Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Thomas Fleming
d7fa0903bc Disable PMP checker to fix test loops 
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
 2021-05-04 01:56:05 -04:00
Domenico Ottolia
2c39c0a6a5 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
David Harris
11ac607723 Removed WALLY-ADD and WALLY-SUB from rv6rp Makefrag that was causing make to break 2021-05-04 00:40:15 -04:00
Domenico Ottolia
84911e6345 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
a7e89f43c1 Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Domenico Ottolia
12d8ff617b Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238 Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9 finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7 updated pipeline tests 2021-05-03 22:07:36 -04:00
Thomas Fleming
f78f2b3b5d Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
Thomas Fleming
5c5f181b7a Get MMU tests working in OVPsim 2021-05-03 21:58:05 -04:00
David Harris
96e90402c5 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
81bfc42be5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:51:54 -04:00
David Harris
062120f944 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
Elizabeth Hedenberg
2358db039d coremark update 2021-05-03 19:42:00 -04:00
David Harris
743011194b Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
4285d60041 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:37:56 -04:00
David Harris
8758b6efa1 Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
08bfaeffe3 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
d06ad058a4 coremark update 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
9e0ce2de61 Coremark objump push 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06 coremark directory changes 2021-05-03 19:35:06 -04:00
David Harris
2f5649832a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:57:36 -05:00
Domenico Ottolia
e59f8037be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:56:05 -04:00
Ross Thompson
21c0ee0cf2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466 Fix bug that caused stvec to get the wrong value 2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4 Implement PMP checker and revise PMA checker 2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033 Remove remnants of InstrReadC 2021-05-03 17:36:25 -04:00
Jarred Allen
a21b84e2ad Add lint to regression 2021-05-03 17:32:05 -04:00