David Harris
68d9c99fba
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
bbracker
54b9745a75
big interrupts refactor
2022-03-30 13:22:41 -07:00
Ross Thompson
3ac736e2d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-30 11:09:44 -05:00
David Harris
049c55769a
fpu compare simplification, minor cleanup
2022-03-29 17:11:28 +00:00
Ross Thompson
7a824eaae1
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
d347de8c49
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
e802deb4d6
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
11e5aad38a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
bdfca503fa
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
50789f9ddd
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
d5f524a15e
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
David Harris
b1340653cf
bit write update
2022-03-09 19:09:20 +00:00
David Harris
004853c312
Refactored SRAM bit write enable
2022-03-09 17:49:28 +00:00
Ross Thompson
acd60218b8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
Ross Thompson
97d64201f7
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
6a52f95cc8
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
ca59778c5a
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
David Harris
caa4d83e57
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
David Harris
f5678e25db
Synthesis cleanup
2022-02-12 06:25:12 +00:00
Ross Thompson
20456097cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
382d5fab0f
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
911ee36b22
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
e0a605e95d
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
cecbb3362d
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
Ross Thompson
d5d9bb9d4d
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
Ross Thompson
3cd067ac6a
Finished merge.
2022-02-08 11:36:24 -06:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
Ross Thompson
1766c0f5ba
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
