Katherine Parry
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66bef379cb
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renamed a file to fit diagram
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2022-07-13 23:44:54 +00:00 |
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Katherine Parry
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3dcddf8453
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some code cleanup
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2022-07-13 15:28:22 -07:00 |
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Katherine Parry
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b874c5c05d
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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b45b3baec2
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removed the +1 in the cvt
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2022-07-13 09:41:35 -07:00 |
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Katherine Parry
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3c1bea1104
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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12a54161c0
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found the bug in the store modification
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2022-07-12 22:42:19 +00:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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1267d33d3c
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forgot a file
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2022-07-11 18:31:51 -07:00 |
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Katherine Parry
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ba339fc794
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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bea4ec078d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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David Harris
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03a20610aa
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added comment about checking SRAM size
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2022-07-10 12:48:51 +00:00 |
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David Harris
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d1a7832dd9
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added comment about RAMs in cacheway
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2022-07-10 12:47:34 +00:00 |
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Katherine Parry
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62205ebb3b
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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c56fdd7e0f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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88b4f9b40a
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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James Stine
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99fed5d59f
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Update SRAM to /proj/wally
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2022-07-08 08:09:55 -05:00 |
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David Harris
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87ea95e6c5
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-08 09:09:07 +00:00 |
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David Harris
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5ae88dbef0
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Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
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2022-07-08 09:09:02 +00:00 |
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David Harris
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96cc66d151
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Adjusting byte writes to RAM
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2022-07-08 08:45:21 +00:00 |
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David Harris
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38ef8eebbb
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Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
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2022-07-08 08:44:37 +00:00 |
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David Harris
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234175f236
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Removed unused swbytemask from CLINT
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2022-07-08 08:43:24 +00:00 |
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Katherine Parry
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b67792086c
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moved unsused division code again
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2022-07-07 16:41:26 -07:00 |
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Katherine Parry
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b1e2a1e5a1
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Revert "moved old divsqrt to unusedsrc"
This reverts commit 5dd07c76bd .
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2022-07-07 16:29:17 -07:00 |
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Katherine Parry
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5dd07c76bd
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moved old divsqrt to unusedsrc
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2022-07-07 16:09:56 -07:00 |
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Katherine Parry
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75a8cea4e4
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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David Harris
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425fec0f41
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 22:00:59 +00:00 |
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Katherine Parry
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c581fba4aa
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modified wally shared
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2022-07-07 21:59:43 +00:00 |
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David Harris
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f865994ba1
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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7771f7b3eb
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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David Harris
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f2915129ab
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Preliminary SRAM integration
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2022-07-07 19:56:20 +00:00 |
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David Harris
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21fb120aac
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 23:43:05 +00:00 |
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Ross Thompson
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d716c25275
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Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
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2022-07-06 18:34:30 -05:00 |
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Madeleine Masser-Frye
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ad29e19a27
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fixed width mismatch for rv64 ieuadrM and readdatawordM
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2022-07-06 22:39:35 +00:00 |
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David Harris
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529f48ed58
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 13:26:26 +00:00 |
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David Harris
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76302a8599
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PLIC and UART passing tests on APB
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2022-07-06 13:26:14 +00:00 |
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Madeleine Masser-Frye
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52562c9190
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new priority onehot module for better area/time
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2022-07-06 00:08:59 +00:00 |
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Madeleine Masser-Frye
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b5454f3a55
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took first match out of pmpadrdec
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2022-07-06 00:02:01 +00:00 |
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Madeleine Masser-Frye
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d8ea12c6f4
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fixed concatenation syntax
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2022-07-05 22:36:54 +00:00 |
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David Harris
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72e216d053
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APB CLINT passing regression
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2022-07-05 15:51:35 +00:00 |
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David Harris
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5f5ad77d4a
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Modified uncore to use AHB bridge to GPIO
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2022-07-05 05:02:21 +00:00 |
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David Harris
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c8ac05ba7b
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AHB bridge for gpio
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2022-07-05 05:01:59 +00:00 |
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David Harris
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ca95b46de5
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Added reference to Schmookler01 for LOA
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2022-07-05 05:01:12 +00:00 |
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David Harris
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1a356312b2
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Added comments to PLIC about likely bug
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2022-07-05 05:00:29 +00:00 |
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David Harris
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abfd935e06
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removed delay in ahblite
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2022-07-05 04:59:28 +00:00 |
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Katherine Parry
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2fc795ca70
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added missing files
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2022-07-03 21:40:47 -07:00 |
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Katherine Parry
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8ac722f693
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Renaming signals to match chapter
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2022-07-03 12:26:22 -07:00 |
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David Harris
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0fa35acbc5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-02 19:37:14 +00:00 |
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David Harris
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89b319aa1b
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FMA ZAligned name
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2022-07-02 19:35:13 +00:00 |
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Katherine Parry
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8930cdcfbb
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some prostprocessing cleanup
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2022-07-01 14:55:46 -07:00 |
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