Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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e603973dff
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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9821a50eaa
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added mstatus uxl, sxl bit tests (not tested in regression yet)
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2022-09-18 00:11:29 +00:00 |
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Kip Macsai-Goren
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0cc7f5719c
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ported endianness tests to 32 bits (not tested in regression yet)
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2022-09-18 00:10:29 +00:00 |
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Kip Macsai-Goren
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c5cbe43732
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Fixed typos in existing endianness test
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2022-09-18 00:09:52 +00:00 |
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Kip Macsai-Goren
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e6987524ab
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added full coverage of subword loads and stores to endianness test
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2022-09-17 23:14:38 +00:00 |
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Kip Macsai-Goren
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cc7d1c8ef9
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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David Harris
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898dbc8e74
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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4fb467ee8a
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Debugging plic-s test
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2022-08-03 13:21:09 +00:00 |
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David Harris
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7e5b78f240
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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David Harris
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cab0349701
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Started plic-s tests
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2022-08-03 03:48:08 +00:00 |
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David Harris
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93d7d7179e
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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David Harris
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429bdae1c4
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Fixed UART reference output
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2022-07-27 22:16:38 +00:00 |
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David Harris
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b08c87cb47
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Finished UART test
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2022-07-27 04:06:59 +00:00 |
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David Harris
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75a265159b
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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slmnemo
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7348af7fd5
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Updated reference file for UART test
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2022-07-26 09:39:31 -07:00 |
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slmnemo
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a9d5805990
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-26 09:15:20 -07:00 |
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slmnemo
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5218865a7f
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Committing changes made to UART test
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2022-07-26 09:14:40 -07:00 |
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David Harris
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2d7f4b133c
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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c6a58eb5b6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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David Harris
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416f5edfe0
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More riscof makefile tuning
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2022-07-25 21:15:56 +00:00 |
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David Harris
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7f7b3359b0
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Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
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2022-07-25 20:50:38 +00:00 |
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slmnemo
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bfced6bfe8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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ca4511b6dc
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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d0aaae26fe
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fixed wally rv32e tests, updated regression makefile to new testflow
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2022-07-22 17:09:46 -07:00 |
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Daniel Torres
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4da96c5791
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fixed 32priv tests, now passing
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2022-07-22 15:35:20 -07:00 |
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Daniel Torres
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24828db612
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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4198145ce2
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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141f2a40e4
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UART updates and PMA fix
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2022-07-22 14:49:03 -07:00 |
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slmnemo
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9cca567136
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Added test comments to reference output
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2022-07-22 12:35:59 -07:00 |
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Daniel Torres
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0e75142ef4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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95fdd408ee
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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slmnemo
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d38369e8bf
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Added new PLIC and UART tests
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2022-07-22 07:12:55 -07:00 |
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slmnemo
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df568fd202
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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Daniel Torres
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8dcb794bbb
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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Daniel Torres
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635a02cf6a
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made makefile more specific, just incase future additions
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2022-07-21 12:50:02 -07:00 |
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Daniel Torres
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a8faddf81f
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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slmnemo
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37bf837d48
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fixed GPIO test by adding a new function to clear PLIC interrupts
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2022-07-19 08:59:16 -07:00 |
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Daniel Torres
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4883bbb952
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-18 12:13:48 -07:00 |
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Daniel Torres
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6a77ada908
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added the sail change to spike to let it all run normally
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2022-07-18 12:13:15 -07:00 |
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Katherine Parry
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ac2ad1d60a
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fixed uncommented line in makefile
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2022-07-14 00:01:07 +00:00 |
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Katherine Parry
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12a54161c0
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found the bug in the store modification
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2022-07-12 22:42:19 +00:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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slmnemo
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e190aeb14b
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Fixed error in gpio test
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2022-07-08 02:27:16 -07:00 |
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Katherine Parry
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7771f7b3eb
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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slmnemo
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4fa4aaa7af
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Resolved conflicts between different gpio files
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2022-07-05 18:38:52 -07:00 |
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slmnemo
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6b2125ab0e
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Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.
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2022-07-05 18:21:17 -07:00 |
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David Harris
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714a3fa962
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Fixed typos in gpio test comments
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2022-07-05 04:57:42 +00:00 |
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David Harris
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8612465756
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fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB
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2022-07-04 03:21:04 +00:00 |
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