15 Commits

Author	SHA1	Message	Date
David Harris	57e1111df3	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
David Harris	c897bef8cd	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
Teo Ene	1d5d7a7840	Flow updated for 90nm	2021-07-01 13:32:42 -05:00
David Harris	aef408af58	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
Katherine Parry	e4db6ea6f5	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
Ross Thompson	db2a38c300	Fixed a few lint errors, ... clock gater was wrong, missing signal definitions in branch predictor.	2021-06-02 09:33:24 -05:00
Ross Thompson	7afbd8d877	The clock gater was not implemented correctly. Now it is level sensitive to a low clock.	2021-06-01 15:05:22 -05:00
Ross Thompson	8e330367ac	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
James E. Stine	889b935630	Modify elements of generics for LZD and shifter wrote for integer ... divider.	2021-05-31 08:36:19 -04:00
Noah Boorstin	2d1f63b590	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
David Harris	6f4e8b723e	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00