Ross Thompson
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5a9e94048a
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The LSU is properly using FlushW rather than TrapM.
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2022-12-22 21:47:34 -06:00 |
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Ross Thompson
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ce7e1073fa
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Success we've replaced TrapM with FlushD in the IFU.
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2022-12-22 21:36:49 -06:00 |
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Ross Thompson
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677f6f8737
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Partial cleanup for BP.
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2022-12-22 20:33:38 -06:00 |
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Ross Thompson
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942acb354e
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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7a0b3d4fc6
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Wavefile updates.
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2022-12-22 19:45:02 -06:00 |
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Kip Macsai-Goren
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964084f0b3
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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a37bde7452
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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Ross Thompson
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47d61984ad
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First pass at resolving ifu flush on trap rather than FlushD.
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2022-12-22 15:53:06 -06:00 |
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David Harris
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567f76c2a5
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Code cleanup
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2022-12-22 10:04:50 -08:00 |
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cturek
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04bc787647
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Added negative-result int diviison support in U and UM registers. 13 tests pass!
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2022-12-22 16:25:37 +00:00 |
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cturek
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1712e69c73
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Moved swap from qslc to otfc
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2022-12-22 15:44:50 +00:00 |
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cturek
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fa03275cca
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-22 05:45:00 +00:00 |
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cturek
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c7d0c8823f
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Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
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2022-12-22 05:44:55 +00:00 |
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David Harris
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4f7d9eee95
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XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 20:39:38 -08:00 |
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Ross Thompson
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b3ff4fe02e
|
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
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2022-12-21 22:13:05 -06:00 |
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cturek
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c405dcf0cb
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worked out some bugs with int div cycles
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2022-12-22 02:22:01 +00:00 |
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cturek
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e441f90b32
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Renamed signals to E and M stages, forwarded preprocessed n to fsm
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2022-12-22 00:43:27 +00:00 |
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Ross Thompson
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d1aa5ba890
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Updated cache fsm names to match book.
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2022-12-21 16:49:53 -06:00 |
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Ross Thompson
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de161c675c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 16:13:09 -06:00 |
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Ross Thompson
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0cb2cf9a5b
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Changed GatedStallF to GatedStallD.
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2022-12-21 16:12:55 -06:00 |
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David Harris
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16c8655161
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 14:12:25 -08:00 |
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David Harris
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a5dc09c97f
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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14444511a5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 14:57:19 -06:00 |
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Ross Thompson
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15042fc856
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Updated fpga constraints.
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2022-12-21 14:50:01 -06:00 |
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cturek
|
2c58fd42db
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-21 20:41:38 +00:00 |
|
David Harris
|
3562542728
|
comment cleanup
|
2022-12-21 12:39:09 -08:00 |
|
David Harris
|
ca949f2110
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
cturek
|
14d9118802
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-21 19:35:57 +00:00 |
|
cturek
|
6761101645
|
fixed normshift calculations
|
2022-12-21 19:35:47 +00:00 |
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David Harris
|
998f446e3c
|
git push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 11:31:27 -08:00 |
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David Harris
|
820e1ab510
|
Removed unused FPU signals
|
2022-12-21 11:31:22 -08:00 |
|
Ross Thompson
|
f6393d1288
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
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Ross Thompson
|
c41d58bd29
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
Ross Thompson
|
2b1e9f8bed
|
The optimzied PC+2/4 logic still hanges on wally32priv.
|
2022-12-21 09:19:34 -06:00 |
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Ross Thompson
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a2329c8e9d
|
Renamed PCPlusUpperF to PCPlus4F.
|
2022-12-21 09:18:30 -06:00 |
|
Ross Thompson
|
a6ffb4cef3
|
Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
|
2022-12-21 09:18:00 -06:00 |
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Ross Thompson
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3fc121ef70
|
Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
|
2022-12-21 09:00:09 -06:00 |
|
Ross Thompson
|
968e174d68
|
Changes to wave file.
|
2022-12-21 08:41:47 -06:00 |
|
Ross Thompson
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bc5d5e902a
|
Comments about PC+2/4.
|
2022-12-21 08:35:43 -06:00 |
|
David Harris
|
28085ce8eb
|
Clean up vecgtored interrupts
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2022-12-20 16:53:09 -08:00 |
|
David Harris
|
88ee834c97
|
Converted tvecmux to structural
|
2022-12-20 16:24:04 -08:00 |
|
Ross Thompson
|
6152c028db
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 18:09:37 -06:00 |
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Ross Thompson
|
2f0d20b8b0
|
privileged pc mux cleanup.
|
2022-12-20 18:05:44 -06:00 |
|
Ross Thompson
|
cba2ed64e5
|
Moved privileged pc logic into privileged unit.
|
2022-12-20 17:55:45 -06:00 |
|
David Harris
|
07dc11a508
|
IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
|
2022-12-20 15:38:30 -08:00 |
|
Ross Thompson
|
b4bdf446cc
|
Implement FENCE.I as NOP when ZIFENCEI is not supported.
|
2022-12-20 17:34:11 -06:00 |
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Ross Thompson
|
d9a1870a31
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 17:11:35 -06:00 |
|
Ross Thompson
|
ef4ecbe62b
|
Changed long names of vectored pcm signals.
|
2022-12-20 17:01:20 -06:00 |
|
David Harris
|
f03d4e6b5a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-20 14:43:33 -08:00 |
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