David Harris
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e65fb5bb35
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Added F_SUPPORTED flag to disable floating point unit when not in MISA
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2021-07-05 10:30:46 -04:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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9927f771cc
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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b84419ff4e
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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David Harris
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718630c378
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Reduced complexity of pmpadrdec
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2021-06-23 03:03:52 -04:00 |
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bbracker
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6e9c6e3e6a
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whoops wavedo typo
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2021-06-20 05:36:54 -04:00 |
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bbracker
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9469367da3
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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3e32ba3684
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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bbracker
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832e4fc7e3
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making linux waveforms more useful
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2021-06-17 08:37:37 -04:00 |
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bbracker
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8338b3bd34
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expanded GPIO testing and caught small GPIO bug
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2021-06-03 10:03:09 -04:00 |
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bbracker
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28abd28b1f
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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a45b61ede9
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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bbracker
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142b02b30a
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improved PLIC test organization
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2021-05-21 15:13:02 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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bbracker
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114bba8370
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small bit of busybear debug progress
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2021-05-19 20:18:00 -04:00 |
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James E. Stine
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97cbdae674
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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Thomas Fleming
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94d734cca9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-05-03 14:02:19 -04:00 |
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bbracker
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1db608fbc6
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small rv64 plic test bugfix
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2021-05-03 10:06:44 -04:00 |
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Thomas Fleming
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10c7260980
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-29 16:30:00 -04:00 |
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Jarred Allen
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c6996ce39d
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Remove signal which no longer exists from default waves, so sim-wally works
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2021-04-29 14:41:10 -04:00 |
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Thomas Fleming
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d29ddddc3f
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Remove unused waves from .do files
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2021-04-29 02:19:46 -04:00 |
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Noah Boorstin
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24bbb674d3
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linux: start using internal branch predictor signal
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2021-04-26 14:34:38 -04:00 |
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Ross Thompson
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44d28dbd1c
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Icache integrated!
Merge branch 'icache-almost-working' into main
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2021-04-26 11:48:58 -05:00 |
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bbracker
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8d77012995
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progress on bus and lrsc
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2021-04-26 07:43:16 -04:00 |
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bbracker
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5687ab1c96
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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Jarred Allen
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59b340dac9
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Merge branch 'main' into cache
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2021-04-19 00:05:23 -04:00 |
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bbracker
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195cead01c
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Jarred Allen
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6ce4d44ae1
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Merge from branch 'main'
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2021-04-08 17:19:34 -04:00 |
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bbracker
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c8c87bd0d8
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merge testbench
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2021-04-08 14:28:01 -04:00 |
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bbracker
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ce7b2314ef
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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James E. Stine
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9026357350
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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ushakya22
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ba01d57767
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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Jarred Allen
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6cda818f09
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Merge branch 'cache2' into cache
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
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2021-03-30 13:32:33 -04:00 |
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Jarred Allen
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85164c7a87
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
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2021-03-30 12:55:01 -04:00 |
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Jarred Allen
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c8a88757ab
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Fix error when reading an instruction that crosses a line boundary
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2021-03-25 18:47:23 -04:00 |
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ShreyaSanghai
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da4086db79
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Removed PCW and InstrW from ifu
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2021-03-26 01:53:19 +05:30 |
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Jarred Allen
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73d4dd8c15
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Begin work on compressed instructions
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2021-03-25 14:43:10 -04:00 |
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Jarred Allen
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feabcf2d50
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Make cache output NOP after a reset
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2021-03-25 13:18:30 -04:00 |
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Jarred Allen
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e8e4e1bee2
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rv64i linear control flow now working
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2021-03-25 13:02:26 -04:00 |
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Jarred Allen
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c16605a105
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Remove deleted signal from waves
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2021-03-23 14:17:17 -04:00 |
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Jarred Allen
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639a718312
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Fix conflicts in ahb-waves that snuck through manual merging
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2021-03-20 17:16:50 -04:00 |
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Jarred Allen
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50c961bbe4
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Merge changes from main
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2021-03-18 18:58:10 -04:00 |
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Jarred Allen
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bf2fbf49ee
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Add icache's read request to ahb wavs
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2021-03-18 18:52:03 -04:00 |
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bbracker
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df51d9908d
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AHB bugfixes and sim waveview refactoring
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2021-03-18 18:25:12 -04:00 |
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bbracker
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11ba96f2e3
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maybe AHB works now
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2021-03-18 17:47:00 -04:00 |
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