435 Commits

Author	SHA1	Message	Date
Ross Thompson	3b327c949f	Minor cleanup of the linux test bench.	2021-08-12 11:14:55 -05:00
Ross Thompson	467e24c05c	Fixed another bug with the atomic instrucitons implemention in the dcache.	2021-08-08 22:50:31 -05:00
Ross Thompson	25533bdc49	Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. ... Fixed logic for trace update in the M and W stages. The M stage should not update if there is an instruction fault.	2021-08-08 00:28:18 -05:00
Ross Thompson	fda9985382	Finally past the CLINT issues.	2021-08-06 16:41:34 -05:00
Ross Thompson	839822d3b1	Now past the CLINT issues.	2021-08-06 16:16:39 -05:00
Ross Thompson	e1319a2fbe	Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.	2021-08-06 16:06:50 -05:00
Ross Thompson	d430659983	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
Ross Thompson	722d298c35	Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.	2021-08-05 16:49:03 -05:00
Ross Thompson	245e7014b3	Added some comments to linux testbench.	2021-07-30 17:57:03 -05:00
Ross Thompson	cd8a66353c	Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.	2021-07-30 14:24:50 -05:00
Ross Thompson	ef66cdeecf	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
Ross Thompson	b9f8c25280	Created new linux test bench and parsing scripts.	2021-07-29 20:26:50 -05:00
Kip Macsai-Goren	8823339aef	added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet	2021-07-23 16:02:42 -04:00
Kip Macsai-Goren	0653630d29	added sfence to legal instructions, zeroed out rom file to populate for tests	2021-07-23 15:55:08 -04:00
Kip Macsai-Goren	f02d52ce50	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-23 15:16:01 -04:00
bbracker	71ef87bc55	testbench workaround for QEMU's SSTATUS XLEN bits	2021-07-23 14:00:44 -04:00
Kip Macsai-Goren	ee1eef3620	include SFENCE.VMA in legal instructions	2021-07-22 20:24:24 -04:00
David Harris	625d925369	Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.	2021-07-22 14:18:27 -04:00
bbracker	70ef670da1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-21 20:07:03 -04:00
bbracker	3c6a1f8824	replace physical address checking with virtual address checking because address translator is broken	2021-07-21 19:47:13 -04:00
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
Katherine Parry	61f81bb76e	FMA parameterized	2021-07-20 22:04:21 -04:00
bbracker	d6c93a50aa	fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk	2021-07-20 17:55:44 -04:00
bbracker	b5ceb6f7c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 15:04:13 -04:00
bbracker	945c8d496f	commented out old hack that used hardcoded addresses	2021-07-20 15:03:55 -04:00
David Harris	62b3673027	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 14:46:58 -04:00
David Harris	20744883df	flag for optional boottim	2021-07-20 14:46:37 -04:00
bbracker	7694342d4e	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
bbracker	761300afcd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 12:08:46 -04:00
David Harris	c117356432	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
bbracker	c9775de3b2	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
bbracker	5347a58192	major fixes to CSR checking	2021-07-20 00:22:07 -04:00
bbracker	aeaf4a31f0	MemRWM shouldn't factor into PCD checking	2021-07-19 18:03:30 -04:00
bbracker	5911029d2b	make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways	2021-07-19 17:11:42 -04:00
bbracker	009e9d97bf	adapt testbench to removal of ReadDataWEn signal	2021-07-19 15:42:14 -04:00
bbracker	02de6014b2	adapt testbench to removal of signal	2021-07-19 15:41:50 -04:00
bbracker	77b690faf0	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
Katherine Parry	8d101548f1	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
bbracker	f4f3ef0307	linux testbench progress	2021-07-18 18:47:40 -04:00
Katherine Parry	3527620c0b	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
Ross Thompson	a0017e39e2	Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.	2021-07-17 21:02:24 -05:00
David Harris	c29a2ff8df	Started atomics	2021-07-17 21:11:41 -04:00
bbracker	6feb95c779	swapped out linux testbench signal names	2021-07-17 14:48:12 -04:00
David Harris	9741b01465	hptw: minor cleanup	2021-07-17 13:40:12 -04:00
David Harris	37cc2ca30f	hptw: factored pregen	2021-07-17 11:11:10 -04:00
David Harris	622a14cbdd	Removed more unused signals from ahblite	2021-07-17 02:21:54 -04:00
Kip Macsai-Goren	3d14d573a0	included virtual memory tests in testbench	2021-07-16 17:57:24 -04:00
Ross Thompson	965f34d78f	Added guide for Ben to do linux conversion.	2021-07-16 15:04:30 -05:00
Ross Thompson	abce241f68	Also changed the shadow ram's dcache copy widths. ... Merge branch 'dcache' into main	2021-07-16 14:21:09 -05:00
Ross Thompson	96aa106852	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00