David Harris
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16a92eaf10
|
Updated testbench assertions.
|
2022-08-23 07:23:24 -07:00 |
|
Ross Thompson
|
ebe4339953
|
Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
|
2022-08-21 15:59:54 -05:00 |
|
Ross Thompson
|
82cce9a627
|
Updated fpga testbench.
|
2022-08-21 14:07:26 -05:00 |
|
Katherine Parry
|
9549c23f45
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
|
Katherine Parry
|
cb0c1b7488
|
radix-2 1 copy passes testfloat
|
2022-08-06 22:54:05 +00:00 |
|
David Harris
|
898dbc8e74
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
257107f908
|
Partitioned fma into separate files
|
2022-08-01 18:07:38 +00:00 |
|
David Harris
|
75a265159b
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
David Harris
|
9ecef0c4cd
|
fixed testbench merge comflict
|
2022-07-26 06:21:46 -07:00 |
|
David Harris
|
2d7f4b133c
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
766252db1b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-25 23:29:08 +00:00 |
|
David Harris
|
5c54c5b521
|
Added rv32f tests to RV64gc
|
2022-07-25 23:29:05 +00:00 |
|
David Harris
|
c6a58eb5b6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
Ross Thompson
|
8193946996
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-23 08:41:59 -05:00 |
|
Katherine Parry
|
b3d932cd61
|
divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
|
Daniel Torres
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24828db612
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
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4198145ce2
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
ba2dcf6da4
|
fixed error in tests.vh
|
2022-07-22 14:55:55 -07:00 |
|
slmnemo
|
ec1ed5bd94
|
Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
|
Daniel Torres
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574e603d69
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 13:52:19 -07:00 |
|
Daniel Torres
|
139e657fcc
|
commented out embench test that should be commented out
|
2022-07-22 13:52:13 -07:00 |
|
slmnemo
|
cb16a75119
|
Added PLIC test to regression
|
2022-07-22 12:35:37 -07:00 |
|
Daniel Torres
|
0e75142ef4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|
Daniel Torres
|
95fdd408ee
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
slmnemo
|
df568fd202
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
|
8dcb794bbb
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
Daniel Torres
|
9421b77613
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-21 12:50:04 -07:00 |
|
Daniel Torres
|
a8faddf81f
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
Katherine Parry
|
fbe8bb2298
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
Katherine Parry
|
7950a675ea
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Daniel Torres
|
5b1adc7a67
|
commented out embench 2.0 tests
|
2022-07-19 13:36:18 -07:00 |
|
Katherine Parry
|
514674417e
|
moved Se into execute stage
|
2022-07-19 01:10:10 +00:00 |
|
Katherine Parry
|
cce5fb8dfd
|
moved Ss to execute stage
|
2022-07-18 20:48:56 +00:00 |
|
Katherine Parry
|
7268b4b334
|
removed underflow from inexactct calculation
|
2022-07-18 17:51:18 +00:00 |
|
Katherine Parry
|
0210718f19
|
renamed signals in ocde to match book
|
2022-07-18 17:31:17 +00:00 |
|
Ross Thompson
|
0ef6137ab9
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
|
2022-07-17 21:05:31 -05:00 |
|
Ross Thompson
|
8356e5d742
|
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
|
Katherine Parry
|
5cb9c9f319
|
merged floating-point radix-2 divider with radix-4
|
2022-07-15 20:16:59 +00:00 |
|
Katherine Parry
|
2fe8b6e34c
|
fixed error in divsqrt
|
2022-07-14 18:16:00 +00:00 |
|
Katherine Parry
|
b874c5c05d
|
removed minus 1 case in rounding
|
2022-07-13 15:01:38 -07:00 |
|
Katherine Parry
|
3c1bea1104
|
removed warnings and took a mux out of the critical path
|
2022-07-12 18:32:17 -07:00 |
|
Katherine Parry
|
18d7fee541
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
Katherine Parry
|
ba339fc794
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-11 18:30:29 -07:00 |
|
Katherine Parry
|
bea4ec078d
|
variable interations implemented in radix-4 divider
|
2022-07-11 18:30:21 -07:00 |
|
DTowersM
|
fe7d03a3da
|
added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
|
Katherine Parry
|
62205ebb3b
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
|
97e7e619d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
Katherine Parry
|
c56fdd7e0f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-08 12:30:50 -07:00 |
|
Katherine Parry
|
88b4f9b40a
|
renamed signals in cvt and prostproc
|
2022-07-08 12:30:43 -07:00 |
|
David Harris
|
8be1dafbd6
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
DTowersM
|
4786fb9fd6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-07 23:11:35 +00:00 |
|
DTowersM
|
aa8580b2dc
|
new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
|
2022-07-07 23:11:02 +00:00 |
|
Katherine Parry
|
75a8cea4e4
|
srt divider merged into fpu
|
2022-07-07 16:01:33 -07:00 |
|
David Harris
|
f865994ba1
|
fixing port errors
|
2022-07-07 21:57:10 +00:00 |
|
Katherine Parry
|
7771f7b3eb
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|
DTowersM
|
5dfff900b1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-06 23:44:27 +00:00 |
|
DTowersM
|
67c5d66209
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
|
2022-07-06 23:43:57 +00:00 |
|
David Harris
|
f5bdbbe219
|
Removed sig4 spurious message from testbench
|
2022-07-05 03:27:14 +00:00 |
|
Katherine Parry
|
2fc795ca70
|
added missing files
|
2022-07-03 21:40:47 -07:00 |
|
Katherine Parry
|
8ac722f693
|
Renaming signals to match chapter
|
2022-07-03 12:26:22 -07:00 |
|
Daniel Torres
|
d1eebac73f
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
|
Daniel Torres
|
2ae22ac6cb
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
slmnemo
|
228028c837
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
Katherine Parry
|
a5fb60eb1a
|
radix-4 early termination working for special cases - not working completely
|
2022-06-27 20:43:55 +00:00 |
|
Katherine Parry
|
70a1bb8377
|
fixed commented out error and removed killprod from result selection
|
2022-06-25 01:42:23 +00:00 |
|
Katherine Parry
|
9eefba5b58
|
added denormal input handeling - radix 4
|
2022-06-24 19:41:40 +00:00 |
|
Katherine Parry
|
de71773d69
|
added radix-4 0/d handling
|
2022-06-23 22:36:19 +00:00 |
|
Katherine Parry
|
a5fc6757a1
|
generate qsel4 in verilog
|
2022-06-23 21:38:04 +00:00 |
|
Katherine Parry
|
d7a363aaa7
|
fixt lint error
|
2022-06-23 16:11:50 +00:00 |
|
Katherine Parry
|
1612daa294
|
Testfloat running division - not passing
|
2022-06-23 00:07:34 +00:00 |
|
David Harris
|
d865a1ce95
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-21 22:45:28 +00:00 |
|
slmnemo
|
80a57d0469
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
b2cea45de0
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
03d823f5d7
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
|
397783812d
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1d4c543f71
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
0ede7c412e
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
475220a5ff
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
David Harris
|
f6e52c7f08
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
DTowersM
|
7c0f4dd954
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 23:34:35 +00:00 |
|
DTowersM
|
39ed36d0ba
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
|
Katherine Parry
|
5f7072bd96
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
DTowersM
|
a61d1ab087
|
simplified coremark
|
2022-06-10 19:15:17 +00:00 |
|
slmnemo
|
a5aa75e5de
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
|
DTowersM
|
1d41e98504
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 23:58:58 +00:00 |
|
DTowersM
|
3d654fd481
|
modified testbench.sv- now works with coremark
|
2022-06-07 23:58:50 +00:00 |
|
DTowersM
|
930c806753
|
cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
|
2022-06-07 23:27:54 +00:00 |
|
DTowersM
|
4cadf139a6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 06:03:19 +00:00 |
|
DTowersM
|
fbfae61ba8
|
added support for 64 bit rv tests
|
2022-06-07 06:02:23 +00:00 |
|
Katherine Parry
|
b8cff98e48
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-06 16:06:54 +00:00 |
|
Katherine Parry
|
eb93bd46d7
|
fma synth warnings and errors removed
|
2022-06-06 16:06:04 +00:00 |
|
slmnemo
|
8c3d7b404b
|
Fixed recurrent issue with testbench where it would never stop
|
2022-06-03 18:56:24 -07:00 |
|
DTowersM
|
23d524b439
|
testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
|
2022-06-03 22:07:14 +00:00 |
|
Katherine Parry
|
5ae63f913a
|
fixed compilation errors
|
2022-06-03 15:34:17 +00:00 |
|
Katherine Parry
|
019994c802
|
removed some debuging code accedentally pushed
|
2022-06-02 22:45:19 +00:00 |
|
slmnemo
|
b35824eadd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-02 12:54:08 -07:00 |
|
Katherine Parry
|
ccda4c771e
|
fpu paramaterized - except fdivsqrt
|
2022-06-02 19:50:28 +00:00 |
|
slmnemo
|
568b83a647
|
Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
This reverts commit 7d2bfb6db8.
|
2022-06-02 12:45:21 -07:00 |
|
slmnemo
|
40abe59d33
|
Revert "Fixed buildroot by adding a second ."
This reverts commit 0982417054.
|
2022-06-02 12:43:59 -07:00 |
|