Ross Thompson
5ebaeb5d90
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
29b3285c8e
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
David Harris
40e0e6a401
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 00:29:12 +00:00
David Harris
d78b806332
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
Ross Thompson
7044277165
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
c1789932a4
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
44b63fc0ba
First cut at moving the dcache bus interface into the LSU.
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Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
David Harris
52469db9ff
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
a7cfda8e52
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
e97e512da9
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
35e31006a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
37b091e5da
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
ae0cc085b4
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
42ad710213
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
Ross Thompson
47638cdccf
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
Ross Thompson
d830721a11
Fixed Type 5b interaction between dcache and hptw.
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This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
82dd41a0fd
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
04d0b85f96
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
fdf493bd47
minro change. comments about needed changes in dcache.
2021-12-19 13:53:02 -06:00
David Harris
da1df17fbb
Do File cleanups
2021-12-17 17:45:26 -08:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
David Harris
b42faa794a
changed ideal memory to MEM_DTIM and MEM_ITIM
2021-12-14 13:05:32 -08:00
David Harris
ee5c2e6101
renamed rv32/64g to rv32/64gc in configuration
2021-12-14 11:22:00 -08:00
David Harris
1ca949c0bb
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
David Harris
d3c3ab3e85
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 05:49:31 -08:00
Ross Thompson
cd59809e42
Fixed numerous errors in the preformance counter updates.
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Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
bbracker
4bc4930ff3
fix recursive signal logging for graphical sims
2021-12-08 16:07:26 -08:00
David Harris
a174c8b4d7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 12:33:59 -08:00
David Harris
5d4014d351
Refactoring ALU and datapath muxes
2021-12-08 12:33:53 -08:00
Ross Thompson
37451b8978
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 13:40:44 -06:00
Ross Thompson
e1249f4312
Updated coremark testbench with the extra ports from FPGA merge.
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Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
bbracker
4060e77b56
increase regression's expectations of buildroot to 246 million
2021-12-08 07:01:22 -08:00
bbracker
ec6c3bd74c
2nd attempt at making regression-wally.py able to be run from a different dir
2021-12-07 13:13:30 -08:00
bbracker
0692372037
attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly
2021-12-07 11:16:43 -08:00
bbracker
8e2a9d5bbb
add buildroot tv linking to make-tests.sh
2021-12-07 11:15:59 -08:00
bbracker
ffe7cf83e5
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
b714490f92
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
d702599d56
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
Ross Thompson
755c3e6a4c
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
David Harris
e4861e11d1
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
Ross Thompson
8e4eacc18e
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
de8e2008d2
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
bbracker
9e4033935f
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
685534fc20
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
