Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
b48d6b5e1f
Solved the sram write first / read first issue. Works correctly with read first now.
2022-09-22 14:16:26 -05:00
Ross Thompson
99e01dd31f
Cleaned up the IFU and LSU around dtim and irom address calculation.
2022-09-21 18:23:56 -05:00
Ross Thompson
980b35d585
Merge branch 'tempMain' into main
2022-09-20 13:57:38 -05:00
Ross Thompson
426ec6222b
Added chip enables to sram.
2022-09-20 10:49:14 -05:00
Ross Thompson
822d989383
Added comment.
2022-09-20 09:49:53 -05:00
Ross Thompson
57c366c1b2
Removed NonIROM and NonDTIM select signals from IFU and LSU.
2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
David Harris
8f2b3b2387
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-15 12:49:21 -07:00
David Harris
94dca9194e
renamed endianswap
2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0
Fixed subword read to work with bigendian.
2022-09-15 14:08:04 -05:00
Ross Thompson
c7d3580637
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
Ross Thompson
7f1ae039b0
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
Ross Thompson
f4e3036593
Oups fixed order of ending swap with mux between cache and fetch buffer.
2022-09-07 16:29:47 -05:00
Ross Thompson
d601fdf186
Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle.
2022-09-02 19:58:41 -05:00
Ross Thompson
055b55402f
clean up subword write.
2022-09-01 17:55:19 -05:00
Ross Thompson
eae56a890c
marked possible improvement to ahb bus fsms.
2022-08-31 23:57:08 -05:00
Ross Thompson
12d1ef2144
More renaming.
2022-08-31 14:49:08 -05:00
Ross Thompson
c03b202ab0
Moved files.
...
Encapsulated ahbinterface.
2022-08-31 14:45:01 -05:00
Ross Thompson
f2f1169a04
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
a0f681944c
More Cleanup.
2022-08-31 11:21:02 -05:00
Ross Thompson
8156109add
More cleanup.
2022-08-31 11:12:38 -05:00
Ross Thompson
89f13370e2
Removed old signals.
2022-08-31 09:50:39 -05:00
Ross Thompson
5409501ca6
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
8b9f30c91a
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
315f662eb9
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c
Progress.
2022-08-30 14:17:00 -05:00
Ross Thompson
8cf3c7b352
new cache bus fsm not working but lints.
...
Forgot a few files in the last commit.
2022-08-30 10:58:07 -05:00
Ross Thompson
a2220fc142
Have a rough working multi manager!
2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c
Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.
2022-08-29 17:04:53 -05:00
Ross Thompson
233777f744
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
Ross Thompson
e805f33f4e
Typo.
2022-08-29 11:40:35 -05:00
Ross Thompson
e7de0e033e
Added comments about planned changes.
2022-08-29 09:48:00 -05:00
Ross Thompson
7b76fbaa9a
Removed ignore request from busfsm.
2022-08-28 21:12:27 -05:00
Ross Thompson
122c88ee46
Created two new pma regions for dtim and irom.
2022-08-28 13:50:50 -05:00
Ross Thompson
dd7736cb93
Possible fix.
2022-08-28 13:10:47 -05:00
Ross Thompson
a81fcc6b4b
Partial fix to bus + dtim.
2022-08-27 23:44:17 -05:00
David Harris
f2517f8290
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
60b673cafd
Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
2022-08-27 05:31:56 -07:00
David Harris
812158aeee
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
95dd50a567
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
David Harris
ca6837f597
Fixed endian swapping on bus only
2022-08-26 19:58:04 -07:00
David Harris
5f37e16b62
Fixed rv32e LSU and IFU issues
2022-08-25 20:02:38 -07:00
David Harris
671ea60f3e
lsu simplification
2022-08-25 18:52:42 -07:00
David Harris
f262abb5c3
Removed unused signals
2022-08-25 18:34:39 -07:00
David Harris
b73286ece6
Removed unused signals
2022-08-25 18:30:46 -07:00
David Harris
cfcde754c3
Removed CacheBusAck
2022-08-25 18:17:34 -07:00
David Harris
9bc62ce124
Removed SelUncachedAdr
2022-08-25 18:15:59 -07:00
David Harris
f39e62eeea
Removed Cache_Enabled
2022-08-25 18:13:34 -07:00
