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216 Commits

Author SHA1 Message Date
Ross Thompson
d545a2ec74 Partially working local history repair. 2023-05-11 14:56:26 -05:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
42517bae6f Fixed bug in local history predictor. 2023-05-04 16:54:41 -05:00
Ross Thompson
ee1e380fad Almost working ahead pipelined local history predictor. 2023-05-04 16:17:31 -05:00
Ross Thompson
8235042ba2 Maybe I finally have the ahead pipelined local history predictor working. 2023-05-04 14:11:34 -05:00
Ross Thompson
060d40853a Ahead pipelining is not yet working. :( 2023-05-03 17:41:38 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
414c79b923 Updated configs for local branch history `defines. 2023-05-02 11:11:04 -05:00
Ross Thompson
08b237b878 Added comment explaining the difference between global history and local history basic implementations. 2023-05-02 11:01:46 -05:00
Ross Thompson
0904a9b97f Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Ross Thompson
4eff75449a Maybe have the baseline local history predictor working. 2023-05-01 15:45:27 -05:00
Ross Thompson
5777b90407 Might actually have a correct implementation of local history branch prediction. 2023-04-24 13:05:28 -05:00
Ross Thompson
e81445be5d Fixed the local branch predictor so that it at least compiles. 2023-04-24 11:06:53 -05:00
Limnanthes Serafini
b3976daccd More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Kevin Thomas
f7838b869b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
2f4074b9c2 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
7ad05d9a42 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Kevin Thomas
4d30aff198 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
0c80067d45 Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
Sydney Riley
55655157ae expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Ross Thompson
366a96a0fc Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Ross Thompson
46b1bca4fc Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
David Harris
e03a533775 Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
a1eccf37dc Fix Issue 145 2023-03-22 04:33:14 -07:00
Ross Thompson
3cae6ca90f Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
ada099c58b Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
a5523400ae Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Ross Thompson
a6b851a672 Renamed signals to be consistent with textbook. 2023-03-06 18:29:31 -06:00
Ross Thompson
31fcc0daf7 Renamed PCFSpill to PCSpillF. 2023-03-06 17:50:57 -06:00
Ross Thompson
473ed2b475 Renamed InstrFirstHalf to InstrFirstHalfF. 2023-03-06 17:48:57 -06:00
Ross Thompson
0cb5369351 Renamed BTB misprediction to BTA. 2023-03-03 00:18:34 -06:00
Ross Thompson
aabb454d1c Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
b98e007a53 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
Ross Thompson
90b2f0a652 Set bp to use instruction class prediction by default. 2023-03-01 11:52:42 -06:00
Ross Thompson
dea6b643a6 Branch predictor cleanup. 
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
 2023-03-01 11:24:24 -06:00
Ross Thompson
03a6679ba0 More btb cleanup. 2023-03-01 10:47:00 -06:00
Ross Thompson
554e7d0973 Minor fix to btb. 2023-03-01 10:45:40 -06:00
Ross Thompson
a6917d07f3 Name cleanup. 2023-02-28 17:48:58 -06:00
Ross Thompson
4c0e7f297a Found the performance bug with the branch predictor btb power saving update. 2023-02-28 15:57:34 -06:00
Ross Thompson
2ebe600f54 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
be4823f7dd Undid the btb update as it reduces performance. 2023-02-28 15:21:56 -06:00
Ross Thompson
9dd3379744 This icpred and btb changes are causing a performance issue. 2023-02-27 20:00:50 -06:00
Ross Thompson
544abe2819 Modified the BTB to save power by not updating when the prediction is unchanged. 2023-02-27 17:37:29 -06:00
Ross Thompson
bc5aecf948 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-27 09:48:03 -06:00
Ross Thompson
318189e5e6 Signal name changes. 2023-02-27 00:39:19 -06:00
Ross Thompson
c89812b2d4 Branch predictor cleanup. 2023-02-26 21:28:36 -06:00
Ross Thompson
e8c5e5b5ff Create module for instruction class prediction and decoding. 2023-02-26 20:20:30 -06:00
David Harris
21b28fd1bb Renamed DAPageFault to UpdateDA 2023-02-26 17:51:45 -08:00
Ross Thompson
72be4318b8 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-26 12:06:06 -06:00
David Harris
35653a18b7 Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED 2023-02-26 09:38:32 -08:00
Ross Thompson
7f8034013d PHT was enabled using the wrong ~flush and ~stall. 2023-02-24 22:57:32 -06:00
Ross Thompson
eb9dc7e67d gshare cleanup. 2023-02-24 22:55:51 -06:00
Ross Thompson
9df05f0b3d More signal renames. 2023-02-24 19:56:55 -06:00
Ross Thompson
8bd4a4c35b Renamed signals to match new figures. 2023-02-24 19:51:47 -06:00
Ross Thompson
f95f326b3d Renamed signals to match figure 10.18. 2023-02-24 19:22:14 -06:00
Ross Thompson
4031b89f18 Possible fix to btb performance issue. 2023-02-24 18:36:41 -06:00
Ross Thompson
ea8cb7dd78 Cleanup. 2023-02-24 18:20:42 -06:00
Ross Thompson
a14dcaa241 Completed critical path gshare fix. 2023-02-24 18:02:00 -06:00
Ross Thompson
31d6531af2 Prep to fix gshare critical path. 2023-02-24 17:54:48 -06:00
Ross Thompson
5db56460b9 Modified btb forwarding logic to reduce critical path. 2023-02-24 17:47:43 -06:00
Ross Thompson
2920179435 Major cleanup of bp. 2023-02-23 16:19:03 -06:00
Ross Thompson
fa49de8391 Partial replacement of InstrClassX with {JalX, RetX, JumpX, and BranchX}. 2023-02-23 15:55:34 -06:00
Ross Thompson
8503982328 Branch predictor cleanup. 2023-02-23 15:15:14 -06:00
Ross Thompson
403b2b7be1 Moved more branch predictor logic into the performance counter block. 2023-02-23 15:14:56 -06:00
Ross Thompson
526f046fb0 Added if generate around bp logic only used with performance counters. 2023-02-23 14:39:31 -06:00
Ross Thompson
2d919fa9e3 Renamed PCPredX to BTAX. 2023-02-23 14:33:32 -06:00
Ross Thompson
c736d7c1f3 Fixed bug in basic gshare. 2023-02-22 12:54:46 -06:00
Ross Thompson
849856034b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-22 09:11:57 -06:00
Ross Thompson
5dde3af22e Oups. Turns out dc_shell does not like string parameters. 
Switched gshare to use an integer parameter to select between gshare and global.
 2023-02-22 09:11:46 -06:00
David Harris
f0566173e6 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-21 09:58:18 -08:00
David Harris
a445e53e8d Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well. 2023-02-21 09:32:17 -08:00
Ross Thompson
7f0d64d0a6 Fixed typo in the global branch predictor. 2023-02-20 18:48:02 -06:00
Ross Thompson
2c2c1b5221 Cleanup branch predictor files. 2023-02-20 18:45:45 -06:00
Ross Thompson
7df3a84060 Renamed branch predictors and consolidated global and gshare predictors. 2023-02-20 18:42:37 -06:00
Ross Thompson
6eefa5b1e3 Fixed another bug in the btb. 2023-02-20 17:54:22 -06:00
Ross Thompson
d2b7047744 Fixed forwarding bug in the BTB. 2023-02-20 17:03:45 -06:00
Ross Thompson
545af7697f Simiplified BTB. 2023-02-20 15:39:42 -06:00
David Harris
36b2d530c4 Merge pull request #98 from ross144/main 
New gshare implementation
 2023-02-20 11:27:47 -08:00
David Harris
626715befd Fixed IROM size parameters 2023-02-20 05:32:43 -08:00
David Harris
472c7da399 New expression for BTB_SIZE to avoid error during sky90 synthesis 2023-02-20 04:02:00 -08:00
Ross Thompson
4db249ca5d Simplified BTB by removing the valid bit. the instruction class provides the equivalent information. 2023-02-19 23:53:20 -06:00
Ross Thompson
407d9e7b4a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-19 22:54:27 -06:00
Ross Thompson
0f98cfe5b4 Simplified branch predictor. 2023-02-19 22:49:48 -06:00
David Harris
d07c6386b2 Added BTB_SIZE parameter independent of BPRED_SIIZE 2023-02-19 20:13:50 -08:00
David Harris
20ced0653c Parameterized btb to depend on BPRED_SIZE 2023-02-19 19:59:07 -08:00
Ross Thompson
89aa57e25e Possibly much better branch predictor implemention. 
The complexity is significantly reduced.
 2023-02-19 00:17:37 -06:00
Ross Thompson
9f997eb5d0 Minor fix. 2023-02-18 23:55:46 -06:00
David Harris
92d4acf118 Removed unused PredInstrClassE register from bpred 2023-02-18 05:59:25 -08:00
Ross Thompson
ae8b01b8d4 Renamed globalhistory predictor. 2023-02-17 16:08:34 -06:00
Ross Thompson
2661ec97d8 Fixed global history predictor. 2023-02-17 16:05:48 -06:00
Ross Thompson
a98a85f144 More updates. 2023-02-17 15:53:49 -06:00
Ross Thompson
1d9335c934 Updated global history predictor. 2023-02-17 15:53:15 -06:00
Ross Thompson
e0a8974c7d Fixed a branch predictor performance issue. 2023-02-17 15:37:03 -06:00
Ross Thompson
3398c5156b Fixed bug with branch predictor. 2023-02-17 10:57:50 -06:00
Ross Thompson
911023f441 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
fc3baa6846 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Ross Thompson
f3c8c6e60a More fixeds to global history. 2023-02-13 18:08:51 -06:00
Ross Thompson
6ea830cf44 Fixed global history predictor. 2023-02-13 18:08:13 -06:00
Ross Thompson
3847d9e39a Updated global history predictor. 2023-02-13 18:07:32 -06:00
Ross Thompson
1ab2d0d19b Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. 2023-02-13 17:57:05 -06:00
Ross Thompson
c18ac35332 Created copy of gshare. I think there may be a simpler implementation. 2023-02-13 17:29:51 -06:00
Ross Thompson
10b45ed6c7 Further branch predictor improvements. 2023-02-13 17:23:56 -06:00
Ross Thompson
1cfdd201a5 Partial improvement. 2023-02-13 17:10:24 -06:00
Ross Thompson
0165fd54b4 Hacked commit. Fixes the gshare bugs introduced last week. 
Need to recover the good changes in the next commit.
 2023-02-13 16:14:17 -06:00
Ross Thompson
716fbca2b1 Partial fix for gshare bugs from the last two weeks. 2023-02-13 11:57:25 -06:00
Ross Thompson
51158e94ba Removed another bit from btb class. 2023-02-12 11:33:43 -06:00
Ross Thompson
91fc883f6a More simplifications to the BP. 2023-02-10 17:09:35 -06:00
Ross Thompson
6fbca64eb7 Experimental branch prediction optimization. 2023-02-10 15:45:56 -06:00
Ross Thompson
ca0eb5a591 Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic. 2023-02-10 10:33:10 -06:00
Ross Thompson
91427ed72d RAS and RAS documentation now consistent. 2023-02-10 09:06:51 -06:00
Ross Thompson
2d7749db7f Updated globalhistory predictor. 2023-02-09 14:48:02 -06:00
Ross Thompson
962c018991 Simplified branch predictor. 2023-02-08 18:24:38 -06:00
Ross Thompson
0678f3f2b7 Branch predictor cleanup. 2023-02-07 14:01:59 -06:00
David Harris
6b9ae4fc89 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00