Rose Thompson
|
5d4a89b27c
|
Fixed bug in the btb branch logging.
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
|
2023-11-15 14:51:47 -06:00 |
|
Rose Thompson
|
feb45b9b59
|
Patched up linux imperas testbench.
|
2023-11-14 14:20:13 -06:00 |
|
Rose Thompson
|
65356e362a
|
Merge branch 'main' of github.com:ross144/cvw
|
2023-11-14 13:54:48 -06:00 |
|
Rose Thompson
|
1c54a5698b
|
Modified the device trees to include all the minor extensions.
|
2023-11-14 13:54:16 -06:00 |
|
Rose Thompson
|
efc1d732d8
|
Fixed the imperas testbench to be compatible with the config changes.
|
2023-11-14 12:57:44 -06:00 |
|
Rose Thompson
|
fdb75203cb
|
Added cbop to to rv32gc.
|
2023-11-14 10:55:22 -06:00 |
|
Rose Thompson
|
d4bc9da085
|
Fixed another bug in the updated script changes.
|
2023-11-13 18:12:02 -06:00 |
|
Rose Thompson
|
919b7cccf1
|
Merge branch 'main' of github.com:ross144/cvw
|
2023-11-13 18:10:35 -06:00 |
|
Rose Thompson
|
f8b65f50b0
|
Fixed bugs in the updated fpga synthe script.
|
2023-11-13 18:10:22 -06:00 |
|
Rose Thompson
|
05eb5460b4
|
Removed fpga config. No longer needed.
|
2023-11-13 17:50:29 -06:00 |
|
Rose Thompson
|
d5f0c15b90
|
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
|
2023-11-13 17:48:28 -06:00 |
|
Rose Thompson
|
95fc5f4a1c
|
Towards removing the FPGA config file.
|
2023-11-13 17:20:26 -06:00 |
|
Rose Thompson
|
6b7ff50a84
|
Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
|
2023-11-13 16:44:02 -06:00 |
|
Rose Thompson
|
a6995af91c
|
Fixed bug in uncore updates which broke SDC.
|
2023-11-13 16:15:23 -06:00 |
|
Rose Thompson
|
707b0c557c
|
Cleanup and optimization of Zicclsm.
|
2023-11-13 14:28:22 -06:00 |
|
Rose Thompson
|
da59cb71a9
|
Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
|
2023-11-13 14:12:27 -06:00 |
|
Rose Thompson
|
540d8d930d
|
Cleanup.
Linux makefile
wally tracer. probably reduce some complexity here.
|
2023-11-13 14:04:43 -06:00 |
|
Rose Thompson
|
1f7d91e8e0
|
Merge branch 'Zicclsm'
|
2023-11-13 13:53:42 -06:00 |
|
Rose Thompson
|
55bcc4dbc1
|
Updates to linux config files for sdc.
|
2023-11-13 13:53:23 -06:00 |
|
Rose Thompson
|
13908ac41c
|
Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.
|
2023-11-13 12:36:32 -06:00 |
|
Rose Thompson
|
cc7a0b211a
|
Cleanup.
|
2023-11-13 12:35:11 -06:00 |
|
Rose Thompson
|
c8cca8dfb8
|
Simplification.
|
2023-11-10 18:39:36 -06:00 |
|
Rose Thompson
|
9dfe421c55
|
Yay! Zicclsm passes my regression test now.
|
2023-11-10 18:28:51 -06:00 |
|
Rose Thompson
|
c0e02ae190
|
Found another bug in the RTL's Zicclsm alignment.
|
2023-11-10 18:26:55 -06:00 |
|
Rose Thompson
|
02ab9fe99c
|
Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
|
2023-11-10 17:58:42 -06:00 |
|
Rose Thompson
|
bd866e1025
|
Fixed some more bugs in the Zicclsm signature.
|
2023-11-10 17:36:10 -06:00 |
|
Rose Thompson
|
efecb0c346
|
Fixed bug in the Zicclsm test.
|
2023-11-10 17:34:23 -06:00 |
|
Rose Thompson
|
84d86b1994
|
Fixed spill bugs in the aligner.
|
2023-11-10 17:18:45 -06:00 |
|
Rose Thompson
|
ada354f443
|
Fixed bug in the misaligned access test.
|
2023-11-10 17:02:15 -06:00 |
|
Rose Thompson
|
b74bfbeefd
|
Merge branch 'main' into Zicclsm
|
2023-11-10 16:15:32 -06:00 |
|
Rose Thompson
|
baacb6f6eb
|
Missed tests.vh.
|
2023-11-10 16:10:10 -06:00 |
|
Rose Thompson
|
9abd26aad9
|
Fixed bug which broke the non Zicclsm configs.
|
2023-11-10 16:08:04 -06:00 |
|
Rose Thompson
|
e1a7c7986a
|
Merge pull request #463 from davidharrishmc/dev
Dev
|
2023-11-10 08:48:07 -08:00 |
|
David Harris
|
426aabbc1a
|
Imperas commenting
|
2023-11-10 08:26:32 -08:00 |
|
David Harris
|
7e00581187
|
Add Svadu support and SPI to imperas configuration
|
2023-11-10 06:27:25 -08:00 |
|
David Harris
|
d7ced56c60
|
Merge pull request #460 from naichewa/main
removed vestigial logic, added comments, deleted unused signals
|
2023-11-10 05:18:57 -08:00 |
|
naichewa
|
5ce16dcb63
|
Cleanup
|
2023-11-09 16:52:55 -08:00 |
|
naichewa
|
3052a68d84
|
Remove old 2/4 bit logic, add comments,
clean up unused signals
|
2023-11-09 16:48:11 -08:00 |
|
David Harris
|
bae3772548
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-11-09 10:33:25 -08:00 |
|
Rose Thompson
|
1d2eccc14d
|
Merge pull request #458 from stineje/main
fix to setup.csh and also ppaSynth.py
|
2023-11-09 10:20:05 -08:00 |
|
David Harris
|
625652b9ca
|
Reporting stall path in synthesis script, support Zcb in Imperas
|
2023-11-09 06:59:29 -08:00 |
|
James E. Stine
|
9a47667fd7
|
update README on ppa
|
2023-11-09 01:00:33 -06:00 |
|
James E. Stine
|
5a115bc6f2
|
update ppaSynth.py with runCommand
|
2023-11-09 00:52:40 -06:00 |
|
James E. Stine
|
a6bc69d73f
|
Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell
|
2023-11-08 23:57:59 -06:00 |
|
David Harris
|
32f68ac4e5
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-11-08 16:06:50 -08:00 |
|
David Harris
|
0e1b4bf8f6
|
Merge pull request #459 from naichewa/main
hardware interlock and hold mode fixes
|
2023-11-08 16:06:39 -08:00 |
|
naichewa
|
b13b8feee4
|
updated to-do comments
|
2023-11-08 15:28:51 -08:00 |
|
naichewa
|
d67badfc60
|
fix hardware interlock, hold mode deassert
|
2023-11-08 15:20:51 -08:00 |
|
James E. Stine
|
41f4c634b0
|
Update to ppaSynth and ppaAnalyze - still have to push in mod for ppaAnalyze to plot more refined plots as well as some other plots - I have a fix working - just need to push in which will do later today
|
2023-11-08 14:00:36 -06:00 |
|
James E. Stine
|
f83188a4a4
|
add typo on setting WALLY for C-shell that caused some incompatability issues
|
2023-11-08 13:59:04 -06:00 |
|