544 Commits

Author	SHA1	Message	Date
slmnemo	5ac17eca1d	Passed Regression: Seems to work perfectly fine	2022-06-09 18:21:13 -07:00
slmnemo	75dffe4dcc	Merge branch 'main' into cacheburstmode	2022-06-09 17:51:03 -07:00
slmnemo	a4c7d1d936	?	2022-06-09 17:50:47 -07:00
slmnemo	c4bc608268	Changes made on 9th Jun	2022-06-09 17:33:51 -07:00
slmnemo	cc8acd947d	Fixed lint error	2022-06-09 17:22:04 -07:00
David Harris	c1a40a15dd	New RAM for further testing	2022-06-09 23:50:43 +00:00
David Harris	5612ca7041	qslc_r4a2 generator	2022-06-09 17:26:47 +00:00
slmnemo	8ae57f075f	Fixed error when doing uncached accesses where HTRANS was always 2	2022-06-08 18:58:07 -07:00
slmnemo	1605544bfc	Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.	2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye	88285c684c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye	a54837b102	added one bit muxes for data critical synths	2022-06-09 00:06:12 +00:00
slmnemo	655266a216	Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending	2022-06-08 15:59:15 -07:00
slmnemo	a64e65e54c	Fixed ifu displaying LSU bus state in wave.do	2022-06-08 15:30:32 -07:00
slmnemo	dd33f2a009	Working version: Fixed error where Word count would always increment even without AHB to bus ACK	2022-06-08 15:29:32 -07:00
slmnemo	be658d3933	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
DTowersM	571eb21f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-06-08 16:28:18 +00:00
DTowersM	38382e3a11	added #1 delays to Stalls and Flushes in hazard unit	2022-06-08 16:28:09 +00:00
slmnemo	a5aa75e5de	Merge branch 'main' into cacheburstmode	2022-06-08 02:21:33 +00:00
slmnemo	1d22fc707a	Added lock signal to ensure AHB speaks with the right bus	2022-06-08 02:19:21 +00:00
David Harris	b53aef33f5	Modified RAM for single-cycle latency	2022-06-08 02:06:00 +00:00
David Harris	cc06fa1c55	Cleaned bram interface	2022-06-08 01:39:44 +00:00
David Harris	f81719337e	Added ahbapbbridge and cleaning RAM	2022-06-08 01:31:34 +00:00
slmnemo	85801e75db	Fixed off-by-one error in busdp capture	2022-06-07 19:36:39 +00:00
slmnemo	90c5e5d319	Reworked bus to handle burst interfacing	2022-06-07 11:22:53 +00:00
Katherine Parry	eb93bd46d7	fma synth warnings and errors removed	2022-06-06 16:06:04 +00:00
Madeleine Masser-Frye	2383ca4f53	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye	6c6a12cfd5	added muxes and inv, fixed priority encoder	2022-06-03 21:03:13 +00:00
Katherine Parry	5ae63f913a	fixed compilation errors	2022-06-03 15:34:17 +00:00
Katherine Parry	c5bde75e30	added createallvectors	2022-06-02 21:56:05 +00:00
Katherine Parry	ccda4c771e	fpu paramaterized - except fdivsqrt	2022-06-02 19:50:28 +00:00
David Harris	9065b684f8	Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit	2022-06-02 09:37:59 -07:00
David Harris	7cf5d481c0	Cleaned up comments in controller	2022-06-02 15:48:33 +00:00
David Harris	129fab3794	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
Katherine Parry	74b549ddc8	paramerterized some small fma units	2022-06-01 23:34:29 +00:00
Katherine Parry	707067548f	unpacker optimizations	2022-06-01 16:52:21 +00:00
slmnemo	108f32e9df	Fixed double assignment on LSUBurstType	2022-06-01 01:04:49 +00:00
slmnemo	56121b3587	Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access	2022-05-31 16:33:05 -07:00
slmnemo	2b80788235	Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode	2022-05-31 15:57:55 -07:00
slmnemo	c24f88c2e9	Redid the FSM to prepare for burst mode implementation	2022-05-31 15:57:42 -07:00
David Harris	efe4b3e8fe	Unpackinput cleanup	2022-05-31 22:31:21 +00:00
David Harris	99da6537cc	Removed normalized output from unpack and simplified interface	2022-05-31 21:32:31 +00:00
David Harris	79df271a6f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-31 21:12:45 +00:00
David Harris	31815422d2	../src/privileged/csrc.sv	2022-05-31 21:12:17 +00:00
Katherine Parry	cd7fe9af61	reorginized unpackinput signals	2022-05-31 17:40:34 +00:00
Katherine Parry	559c0c278e	added unpackinput.sv	2022-05-31 16:18:50 +00:00
David Harris	2935188035	Moved delegation logic from privmode to trap to simplify interface	2022-05-31 14:58:11 +00:00
David Harris	d1ef3b8981	Removed unused fp add and convert modules	2022-05-29 23:07:56 +00:00
Katherine Parry	835a4e4606	fixed lint error	2022-05-28 10:20:13 -07:00
slmnemo	f426850bc7	Reverted incorrect Ack	2022-05-28 10:06:26 +00:00
David Harris	80315fedff	fixed merge conflicts	2022-05-28 09:44:55 +00:00