Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
631 Commits 5 Branches 2 Tags 53 MiB
59b340dac9
Commit Graph

62 Commits

Author SHA1 Message Date
Noah Boorstin
5902637632 buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
a149f2f3d8 Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Shreya Sanghai
75caa65df1 Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
Shreya Sanghai
3696bf4f2c fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Teo Ene
6aed8eaea1 Updated MISA in coremark_bare config file 2021-03-31 20:39:02 -05:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Teo Ene
07f7df82e3 Added BPTYPE to coremark_bare config 2021-03-24 16:38:29 -05:00
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Noah Boorstin
847bf0b9a6 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3 everyone gets a bootram 2021-03-18 12:35:37 -04:00
Noah Boorstin
a226e24ed3 busybear: update memory map, add GPIO 2021-03-18 12:17:35 -04:00
Teo Ene
083a24c06b addition to last commit 2021-03-17 14:52:31 -05:00
Elizabeth Hedenberg
74ebe0bef2 replicating coremark changes into coremark bare 2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
a3b2ffb2c9 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Noah Boorstin
162955de69 busybear: add COUNTERS define 2021-03-16 21:08:47 -04:00
Shreya Sanghai
d9b1e7d67f added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Shreya Sanghai
518618ad38 Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
ca2a65770c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Noah Boorstin
0af002eb2f busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Shreya Sanghai
7cd8f1a592 added performance counters 2021-03-04 11:42:52 -05:00
Teo Ene
2723b21988 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
80f6d6c944 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Teo Ene
0c009fb1e6 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches 2021-03-04 01:27:05 -06:00
Noah Boorstin
f11b3108d8 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
Noah Boorstin
2769b147cb busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489 busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Teo Ene
b9701293a0 Changed TIMBASE in coremark config file 2021-02-25 11:03:41 -06:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
David Harris
adc5d5bc1a Added MUL 2021-02-15 22:27:35 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00
Brett Mathis
11e2666bb2 Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00