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383 Commits

Author SHA1 Message Date
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
350fdd944d Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit fb221d7b64.
 2022-12-04 00:01:58 +00:00
cturek
fb221d7b64 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
David Harris
db5f3c15a4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
6079a01bc8 update test list 2022-12-02 04:28:47 -08:00
David Harris
0d23ab3ec1 reorder tests 2022-12-01 16:27:33 -08:00
David Harris
3a8602523e FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
2f582cd91f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
cedb234013 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
cturek
10c2d45888 div tests in sim-wally 2022-11-30 02:32:04 +00:00
Kip Macsai-Goren
44ea8d8b22 added failing satp invalid tests to regression 2022-11-29 10:43:38 -08:00
cturek
78c2ce5649 Updated testbench/wave for fdivsqrt new start signals 2022-11-22 22:22:26 +00:00
cturek
9d30a832c3 Reoredered tests for arch32m 2022-11-09 18:42:00 +00:00
cturek
2cbe2fd70b Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
David Harris
53a88fec8f Reorder embench tests to prevent crash 2022-11-04 15:21:51 -07:00
Ross Thompson
a59df0c77d Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
David Harris
e49e99548a Fixed testbench-fp to support all again 2022-09-21 13:19:48 -07:00
David Harris
030fb79a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 10:35:11 -07:00
David Harris
cb4c3ff1ce Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
Ross Thompson
ac864a6ca3 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
David Harris
87cde2c427 make QmM size b+1 indpenedent of radix 2022-09-20 03:25:09 -07:00
David Harris
8e90862dad Removed EarlyTermShift from fdiv 2022-09-19 08:44:23 -07:00
David Harris
498c053aab FP testbench 2022-09-18 21:27:21 -07:00
David Harris
f38bb5b32e Divide testfloat starts with half-precision tests 2022-09-18 06:46:47 -07:00
Kip Macsai-Goren
cc7d1c8ef9 Created initial endianness tests 2022-09-16 01:06:26 +00:00
Ross Thompson
c7d3580637 Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
David Harris
c730ddf74a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 11:11:39 -07:00
David Harris
7a29f9c95b Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
Ross Thompson
0615798467 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
David Harris
ce6e153b15 Run 16-bit fsqrt tests first 2022-09-07 10:26:09 -07:00
Ross Thompson
3571fb18c2 Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
DTowersM
48a1abf06f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-31 00:18:04 +00:00
DTowersM
bdeb5c6509 fixed qrduino keyerror in embench test 2022-08-31 00:17:58 +00:00
David Harris
e1760dde55 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
David Harris
2788022c22 renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
Ross Thompson
db635e3ad2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
179aec3616 Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
Ross Thompson
3b612d6201 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
b0aea77b20 Added generate around uncore. 2022-08-25 10:35:24 -05:00
David Harris
f7209627c2 removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
562be633ab Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
fc22e807e2 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
4a371b6829 added SD card and external ram to common testbench. 2022-08-24 13:27:18 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
7fcc852687 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
16a92eaf10 Updated testbench assertions. 2022-08-23 07:23:24 -07:00
Ross Thompson
ebe4339953 Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
82cce9a627 Updated fpga testbench. 2022-08-21 14:07:26 -05:00
Katherine Parry
9549c23f45 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
cb0c1b7488 radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
257107f908 Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
9ecef0c4cd fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
766252db1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
5c54c5b521 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
ba2dcf6da4 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
ec1ed5bd94 Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
Daniel Torres
574e603d69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
139e657fcc commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
cb16a75119 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
8dcb794bbb added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
9421b77613 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 12:50:04 -07:00
Daniel Torres
a8faddf81f removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
7950a675ea added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Daniel Torres
5b1adc7a67 commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Katherine Parry
514674417e moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
cce5fb8dfd moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
0210718f19 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
0ef6137ab9 Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
8356e5d742 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
Katherine Parry
5cb9c9f319 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
2fe8b6e34c fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
b874c5c05d removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
3c1bea1104 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
ba339fc794 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
bea4ec078d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00