David Harris
7705209141
Merged PR#37 branch predictor
2023-01-29 14:25:28 -08:00
Ross Thompson
a9902337cf
Merge branch 'main' of https://github.com/openhwgroup/cvw
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This merges the branch predictor improvements into the main repo.
2023-01-29 15:24:20 -06:00
David Harris
2a20d71a12
Missing files related to rv32imc config
2023-01-29 11:40:08 -08:00
Madeleine Masser-Frye
6ece31183c
Fixed config file writing for synthesis ( #29 )
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* Fixed writing config files for synth sweeps
* cleaned up comments
2023-01-26 06:58:15 +02:00
Ross Thompson
9c83b2dff5
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
5b740fbf60
Removed SDC from repo due to copy right issue.
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Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
eroom1966
43d5769bd9
update
2023-01-19 13:29:46 +00:00
eroom1966
7a4472f94e
ignore external
2023-01-18 13:22:32 +00:00
David Harris
d6aad0f3c3
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
2022-12-27 21:24:38 -08:00
Ross Thompson
6f6cda5f0e
Added files to gitignore.
2022-12-18 18:53:37 -06:00
David Harris
97a432570a
Regression delete wkdir files to prevent spurious failures
2022-12-15 10:24:58 -08:00
Daniel Torres
d0aaae26fe
fixed wally rv32e tests, updated regression makefile to new testflow
2022-07-22 17:09:46 -07:00
Daniel Torres
c29a60c198
changed gitignore, updated version of arch tests on main build
2022-07-21 21:10:15 -07:00
Madeleine Masser-Frye
3b73600932
organized ppa files into ppa directory
2022-07-05 22:28:25 +00:00
Madeleine Masser-Frye
1b0516a863
organizing synth scripts
2022-06-24 06:43:44 +00:00
Madeleine Masser-Frye
855deafce5
ignore folder of PPA synth runs
2022-06-24 00:22:57 +00:00
Daniel Torres
475220a5ff
arch bug fixes and testbench changes
2022-06-17 15:07:16 -07:00
Daniel Torres
cd56d256ad
added new work files to gitignore
2022-06-16 18:06:25 -07:00
DTowersM
a229e0ee87
fixed typo in git ignore
2022-06-13 23:34:27 +00:00
DTowersM
12f465ea05
added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
2022-06-13 23:33:10 +00:00
David Harris
5612ca7041
qslc_r4a2 generator
2022-06-09 17:26:47 +00:00
Madeleine Masser-Frye
0ef0c5498a
stop tracking runArchive and ppa plots
2022-06-03 22:03:26 +00:00
David Harris
4335895b21
Added comments to some files, added a+b = 0 detector to comparator.sv
2022-05-28 09:41:48 +00:00
David Harris
7aba83a35c
Cleaned up unpacker changes in srt and lint errors
2022-05-17 00:06:14 +00:00
David Harris
52e260c146
Ignore intermediate files in synthesis sweeps
2022-04-27 13:12:04 +00:00
David Harris
c22d6f2848
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
bbracker
8321c76d95
greatly improve trace-generating checkpoint process with QEMU hack
2022-02-28 23:00:00 +00:00
David Harris
ec27df6a12
Enhanced printing intermediate results in fpcalc.c
2022-02-28 04:15:20 +00:00
David Harris
30b0f21255
New softfloat_calc program
2022-02-27 20:35:01 +00:00
David Harris
bb14dba9be
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
bbracker
e9e358cdd0
revived checkpointing and hacked it up to generate a trace starting at the checkpoint
2022-02-25 23:51:40 +00:00
Ross Thompson
21364dae32
Ignore saif files.
2022-02-09 19:30:26 -06:00
bbracker
05dd37d3d6
rename dump-dts debug script
2022-02-10 00:10:09 +00:00
Ross Thompson
ed4e912413
Cleaned up synthesis flow.
2022-02-09 15:18:49 -06:00
bbracker
f642e4fb2c
gitignore dtb's because we only care about dts's as being source files
2022-02-08 11:14:59 +00:00
bbracker
b165fe3937
add trimmed-down virt devicetree to repo for QEMU
2022-02-08 11:11:44 +00:00
David Harris
dd26e9e87e
ignore .sv files in synthDC/hdl
2022-02-04 00:57:13 +00:00
David Harris
ee315bd62b
examples cleanup
2022-02-02 12:57:13 +00:00
David Harris
2d112698b7
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
David Harris
c6adb7b6b1
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
David Harris
8b62130070
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
David Harris
ea42025901
Fixed .gitignore
2021-12-29 18:58:36 +00:00
Ross Thompson
0e9e561726
Updated .gitignore file to hide fpga outputs.
2021-12-13 18:30:10 -06:00
David Harris
19fb0aace8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
83765ea3bc
Added files to repo
2021-12-04 20:25:33 -08:00
Ross Thompson
7f52d86980
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
bbracker
8563c0f016
linux testgen refactor
2021-11-01 14:09:49 -07:00
bbracker
ca61d9b6b8
gitignore the addins folder because it contains external repos
2021-10-19 13:32:26 -07:00
bbracker
f2cab415b2
gitignore new logs folder
2021-10-12 10:42:13 -07:00
bbracker
56f246463f
separated buildroot debugging from buildroot logging
2021-07-17 14:52:34 -04:00
bbracker
04ce2f7256
testvector unlinker for dev purposes
2021-07-14 11:05:34 -04:00
bbracker
eb8c1bf5e7
needed to create a directory for gdb script
2021-07-13 19:39:57 -04:00
bbracker
90eb84cc61
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
bbracker
b2cb86d55c
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
bbracker
5736fdecbb
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
bbracker
59b2a49854
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
bbracker
3ae4cd951a
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
56b0d4d016
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
bracker
3d99c9c2c4
gitignore merge
2021-06-18 21:12:05 -05:00
bracker
ed75172f21
handle tera usernames more gracefully
2021-06-18 21:11:14 -05:00
bbracker
10ca2ac5bc
on-Tera solution for sym linking to linux testvectors
2021-06-18 22:01:18 -04:00
bracker
a9f9ef1180
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 20:41:01 -05:00
bracker
8a8b0dcfd7
script support for copying large files from tera
2021-06-18 20:40:19 -05:00
bbracker
7de660f8aa
still not sure if QEMU workaround is correct, but here is all linux progress so far
2021-06-17 00:50:02 -04:00
bbracker
c08f5e6732
script for running make and logging output
2021-05-17 22:12:18 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Noah Boorstin
0e71c212b2
buildroot parser: more updates
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5 -> 23 instructions!
2021-04-17 17:44:46 -04:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Noah Boorstin
ed37e933e5
busybear: stop NOPing out atomics
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and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Thomas Fleming
95bf1e26b8
Add vscode and pycache folders to .gitignore
2021-03-25 02:37:50 -04:00
bbracker
77768cee5d
gitignore FunctionRadix.addr
2021-03-25 00:13:46 -04:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
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Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Noah Boorstin
a5f1dbfe23
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
Jarred Allen
b57604f4e4
Add the regression logs and new regression byproducts to the gitignore
2021-02-02 10:43:41 -05:00
Noah Boorstin
be3d024527
Busybear test now processes first 100 instrs correctly!
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- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
6d88c57f0f
load instructions from file line by line
2021-01-22 14:11:17 -05:00
Noah Boorstin
3f2820646d
More testbench setup work
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- Copy bare-bones testbench from E85
- have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
- Create .gitignore for vsim files
- Make PC reset a macro, change to 0x1000 to conform to the bootloader
I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo
for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 17:55:05 -05:00
