16 Commits

Author	SHA1	Message	Date
Ross Thompson	5591b447d6	Fixed more issues with arty a7 constarints.	2023-04-16 13:25:02 -05:00
Ross Thompson	777edb0fcd	Progress on arty a7 board.	2023-04-13 17:57:12 -05:00
Ross Thompson	e490ab09cf	Updated to help debut Jacob's crossbar woes.	2023-04-11 14:22:42 -05:00
Ross Thompson	9d9c2b170d	Finally building ddr3 xilinx ip from script.	2023-04-10 14:36:33 -05:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
Ross Thompson	0ed9811e31	Updated fpga constraints.	2023-01-20 20:16:33 -06:00
Ross Thompson	9c83b2dff5	Updated ignore to exclude copied files.	2023-01-20 19:47:33 -06:00
Ross Thompson	25bd2e4670	Removed mark_debug vivado directive from source code. ... Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory.	2023-01-20 19:43:18 -06:00
Ross Thompson	5b740fbf60	Removed SDC from repo due to copy right issue. ... Modified fpga build flow to reference it outside the repo.	2023-01-20 14:57:06 -06:00
Ross Thompson	15042fc856	Updated fpga constraints.	2022-12-21 14:50:01 -06:00
Ross Thompson	5c49cc4dd0	Fixed bug with fpga makefile.	2022-11-07 09:20:05 -06:00
Ross Thompson	9ba487c323	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
Ross Thompson	bb79f70a63	Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.	2021-12-12 17:21:44 -06:00
Ross Thompson	35dd1b5c9f	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
Ross Thompson	7f52d86980	Added make clean to fpga IP generator.	2021-11-29 18:42:28 -06:00
Ross Thompson	1117b90f40	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00